| #
a117f09b |
| 19-Oct-2017 |
Bin Meng <bmeng.cn@gmail.com> |
UPSTREAM: spi: ich: Lock down controller settings if required
Some Intel FSP (like Braswell) does SPI lock-down during the call to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done, it's
UPSTREAM: spi: ich: Lock down controller settings if required
Some Intel FSP (like Braswell) does SPI lock-down during the call to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done, it's bootloader's responsibility to configure the SPI controller's opcode registers properly otherwise SPI controller driver doesn't know how to communicate with the SPI flash device.
Rather than passively doing the opcode configuration, let's add a simple DTS property "intel,spi-lock-down" and let the driver call the opcode configuration function if required by such FSP.
Change-Id: I2cef052b87320392449c39a8aa2330236539a2c3 Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> (cherry picked from commit ab20107468de5bf6b9affa93b17f2284cc838b5b)
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| #
41a85fe3 |
| 03-Sep-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
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| #
d2ca80c3 |
| 27-Aug-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ich-spi: Clear atomic preop only when SPI settings are not locked
The atomic preop register can only be written when SPI settings are not locked, otherwise it's read-only.
Signed-off-by: Bin M
x86: ich-spi: Clear atomic preop only when SPI settings are not locked
The atomic preop register can only be written when SPI settings are not locked, otherwise it's read-only.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
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| #
52dd56ba |
| 27-Aug-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ich-spi: Remove useless assignment in ich_spi_xfer()
In ich_spi_xfer() when the driver presets control fields, control variable gets assigned twice. Apparently only the last assignment takes ef
x86: ich-spi: Remove useless assignment in ich_spi_xfer()
In ich_spi_xfer() when the driver presets control fields, control variable gets assigned twice. Apparently only the last assignment takes effect. Remove the other one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
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| #
0031af9c |
| 26-Aug-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
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| #
b42711f9 |
| 16-Aug-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ich-spi: Move opcode registers configuration to another routine
At present the ICH SPI opcode registers configuration is done in the ich_spi_remove() routine, a little bit weird but that's how
x86: ich-spi: Move opcode registers configuration to another routine
At present the ICH SPI opcode registers configuration is done in the ich_spi_remove() routine, a little bit weird but that's how current. Linux MTD driver works. This changes to move the opcode registers configuration to a separate routine ich_spi_config_opcode() which might be called by U-Boot itself as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
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| #
3e791416 |
| 16-Aug-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ich-spi: Don't read cached lock status
At present the ICH SPI controller driver reads the controller lock status from its register in the probe routine and saves the lock status to a member of
x86: ich-spi: Don't read cached lock status
At present the ICH SPI controller driver reads the controller lock status from its register in the probe routine and saves the lock status to a member of priv. Later the driver uses the cached status from priv to judge whether the controller setting is locked and do different setup.
But such logic is only valid when there is only the SPI controller driver that touches the SPI hardware. In fact the lock status change can be trigged outside the driver, eg: during the fsp_notify() call when Intel FSP is used.
This changes the driver to read the lock status every time when an SPI transfer is initiated instead of reading the cached one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
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| #
7d829789 |
| 16-Aug-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ich-spi: Remove unnecessary assignment in ich_init_controller()
There is no need to do another assignment to ich7_spi.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <s
x86: ich-spi: Remove unnecessary assignment in ich_init_controller()
There is no need to do another assignment to ich7_spi.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
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| #
94bc9177 |
| 16-Aug-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ich-spi: Remove spi_write_protect_region()
This routine is not called anywhere.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
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| #
ae1b9399 |
| 17-May-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
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| #
4759dffe |
| 24-Apr-2017 |
Stefan Roese <sr@denx.de> |
spi: ich: Configure SPI BIOS parameters for Linux upon U-Boot exit
This patch adds a remove function to the Intel ICH SPI driver, that will be called upon U-Boot exit, directly before the OS (Linux)
spi: ich: Configure SPI BIOS parameters for Linux upon U-Boot exit
This patch adds a remove function to the Intel ICH SPI driver, that will be called upon U-Boot exit, directly before the OS (Linux) is started. This function takes care of configuring the BIOS registers in the SPI controller (similar to what a "standard" BIOS or coreboot does), so that the Linux MTD device driver is able to correctly read/write to the SPI NOR chip. Without this, the chip is not detected at all.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Jagan Teki <jteki@openedev.com>
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| #
21342d4a |
| 08-Feb-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
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| #
e160f7d4 |
| 17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree,
dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| #
19d051a2 |
| 22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi
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| #
08fe9c29 |
| 08-Aug-2016 |
Jagan Teki <jteki@openedev.com> |
spi: Use mode for rx mode flags
Make rx mode flags as generic to spi, earlier mode_rx is maintained separately because of some flash specific code.
Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <
spi: Use mode for rx mode flags
Make rx mode flags as generic to spi, earlier mode_rx is maintained separately because of some flash specific code.
Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
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| #
3e389d8b |
| 01-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pch: Rename get_sbase op to get_spi_base
Spell out 'sbase' to 'spi_base' so that it looks clearer.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Teste
dm: pch: Rename get_sbase op to get_spi_base
Spell out 'sbase' to 'spi_base' so that it looks clearer.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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| #
6e670b5c |
| 01-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
spi: ich: Change PCHV_ to ICHV_
The ICH SPI controller supports two variants, one of which is ICH7 compatible and the other is ICH9 compatible. Change 'pch_version' to 'ich_version' to better match
spi: ich: Change PCHV_ to ICHV_
The ICH SPI controller supports two variants, one of which is ICH7 compatible and the other is ICH9 compatible. Change 'pch_version' to 'ich_version' to better match its original name.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
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| #
1f9eb59d |
| 01-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
spi: ich: Use compatible strings to distinguish controller version
At present ich spi driver gets the controller version information via pch, but this can be simply retrieved via spi node's compatib
spi: ich: Use compatible strings to distinguish controller version
At present ich spi driver gets the controller version information via pch, but this can be simply retrieved via spi node's compatible string.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
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| #
9eb4339b |
| 01-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
spi: ich: Some clean up
This cleans up the ich spi driver a little bit: - Remove struct ich_spi_slave that is not referenced anywhere - Remove ending period in some comments - Move struct ich_spi_pl
spi: ich: Some clean up
This cleans up the ich spi driver a little bit: - Remove struct ich_spi_slave that is not referenced anywhere - Remove ending period in some comments - Move struct ich_spi_platdata and struct ich_spi_priv to ich.h - Add #ifndef _ICH_H_ .. in ich.h
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
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| #
f2b85ab5 |
| 19-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API.
In addition the driver
dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device.
Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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| #
fffe25db |
| 19-Jan-2016 |
Simon Glass <sjg@chromium.org> |
spi: ich: Separate out the read/write trace from normal debugging
The trace is seldom useful for basic debugging. Allow it to be enabled separately so that it is easier to see the more important ini
spi: ich: Separate out the read/write trace from normal debugging
The trace is seldom useful for basic debugging. Allow it to be enabled separately so that it is easier to see the more important init and error debug messages.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| #
91292e0b |
| 16-Dec-2015 |
Jagan Teki <jteki@openedev.com> |
spi: Rename op_mode_rx to mode_rx
Since spi rx mode macro's are renamed to simple and meaninfull, this patch will rename the respective structure members.
Cc: Simon Glass <sjg@chromium.org> Cc: Bin
spi: Rename op_mode_rx to mode_rx
Since spi rx mode macro's are renamed to simple and meaninfull, this patch will rename the respective structure members.
Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
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| #
e5961f07 |
| 16-Dec-2015 |
Jagan Teki <jteki@openedev.com> |
spi: Rename SPI_OPM_RX_* to SPI_RX_*
SPI_OPM_RX_AS - SPI_RX_SLOW SPI_OPM_RX_AF - SPI_RX_FAST SPI_OPM_RX_DOUT - SPI_RX_DUAL SPI_OPM_RX_QOF - SPI_RX_QUAD
Cc: Simon Glass <sjg@chromium.org> Cc: Micha
spi: Rename SPI_OPM_RX_* to SPI_RX_*
SPI_OPM_RX_AS - SPI_RX_SLOW SPI_OPM_RX_AF - SPI_RX_FAST SPI_OPM_RX_DOUT - SPI_RX_DUAL SPI_OPM_RX_QOF - SPI_RX_QUAD
Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
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| #
cdf33938 |
| 13-Dec-2015 |
Jagan Teki <jteki@openedev.com> |
spi: Rename SPI_TX_BP|QPP to SPI_TX_BYTE|QUAD
Since SPI_TX_* are spi_slave{} members so use spi protocol notation instead spi flash programming, like
SPI_TX_BP => SPI_TX_BYTE SPI_TX_QPP => SPI_TX_
spi: Rename SPI_TX_BP|QPP to SPI_TX_BYTE|QUAD
Since SPI_TX_* are spi_slave{} members so use spi protocol notation instead spi flash programming, like
SPI_TX_BP => SPI_TX_BYTE SPI_TX_QPP => SPI_TX_QUAD
Cc: Simon Glass <sjg@chromium.org> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
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| #
095a41d3 |
| 13-Dec-2015 |
Jagan Teki <jteki@openedev.com> |
spi: Use mode instead of op_mode_tx
Used mode member from spi_slave{} instead of op_mode_tx.
Cc: Simon Glass <sjg@chromium.org> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng
spi: Use mode instead of op_mode_tx
Used mode member from spi_slave{} instead of op_mode_tx.
Cc: Simon Glass <sjg@chromium.org> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
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