Searched hist:"6 de9b3364b458160c1229d00667caf93ba93c097" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch32/ |
| H A D | cortex_a72.S | 6de9b3364b458160c1229d00667caf93ba93c097 Wed Aug 02 17:33:41 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A72: Implement workaround for erratum 859971
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|
| /rk3399_ARM-atf/include/lib/cpus/aarch32/ |
| H A D | cortex_a72.h | 6de9b3364b458160c1229d00667caf93ba93c097 Wed Aug 02 17:33:41 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A72: Implement workaround for erratum 859971
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a72.h | 6de9b3364b458160c1229d00667caf93ba93c097 Wed Aug 02 17:33:41 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A72: Implement workaround for erratum 859971
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a72.S | 6de9b3364b458160c1229d00667caf93ba93c097 Wed Aug 02 17:33:41 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A72: Implement workaround for erratum 859971
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 6de9b3364b458160c1229d00667caf93ba93c097 Wed Aug 02 17:33:41 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A72: Implement workaround for erratum 859971
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|