Searched hist:"6 c70935d7525a4b2b144b49457d2bae85f1d111a" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/ |
| H A D | emif.h | 6c70935d7525a4b2b144b49457d2bae85f1d111a Fri Nov 08 12:10:37 UTC 2013 SRICHARAN R <r.sricharan@ti.com> ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap5/ |
| H A D | omap.h | 6c70935d7525a4b2b144b49457d2bae85f1d111a Fri Nov 08 12:10:37 UTC 2013 SRICHARAN R <r.sricharan@ti.com> ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
|