Searched hist:"65 d297af7c6a08ec65bf005fa9bd5cdb955efe39" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/mips/include/asm/ |
| H A D | mipsregs.h | 65d297af7c6a08ec65bf005fa9bd5cdb955efe39 Sun Feb 07 23:37:59 UTC 2016 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> MIPS: fix iand optimize setup of CP0 registers
Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.
Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.
Initialize cp0 count as early as possible to get the most
accurate boot timing.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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| /rk3399_rockchip-uboot/arch/mips/cpu/ |
| H A D | start.S | 65d297af7c6a08ec65bf005fa9bd5cdb955efe39 Sun Feb 07 23:37:59 UTC 2016 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> MIPS: fix iand optimize setup of CP0 registers
Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.
Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.
Initialize cp0 count as early as possible to get the most
accurate boot timing.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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