Searched hist:"5 f06bffa831638fd95d2160209000ef36d2a22ce" (Results 1 – 6 of 6) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/n5x/include/ |
| H A D | n5x_clock_manager.h | 5f06bffa831638fd95d2160209000ef36d2a22ce Thu Dec 22 13:52:36 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> fix(intel): fix Agilex and N5X clock manager to main PLL C0
Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19
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| /rk3399_ARM-atf/plat/intel/soc/n5x/soc/ |
| H A D | n5x_clock_manager.c | 5f06bffa831638fd95d2160209000ef36d2a22ce Thu Dec 22 13:52:36 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> fix(intel): fix Agilex and N5X clock manager to main PLL C0
Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19
|
| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | agilex_clock_manager.h | 5f06bffa831638fd95d2160209000ef36d2a22ce Thu Dec 22 13:52:36 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> fix(intel): fix Agilex and N5X clock manager to main PLL C0
Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19
|
| /rk3399_ARM-atf/plat/intel/soc/stratix10/soc/ |
| H A D | s10_clock_manager.c | 5f06bffa831638fd95d2160209000ef36d2a22ce Thu Dec 22 13:52:36 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> fix(intel): fix Agilex and N5X clock manager to main PLL C0
Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19
|
| /rk3399_ARM-atf/plat/intel/soc/agilex/soc/ |
| H A D | agilex_clock_manager.c | 5f06bffa831638fd95d2160209000ef36d2a22ce Thu Dec 22 13:52:36 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> fix(intel): fix Agilex and N5X clock manager to main PLL C0
Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19
|
| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | platform_def.h | 5f06bffa831638fd95d2160209000ef36d2a22ce Thu Dec 22 13:52:36 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> fix(intel): fix Agilex and N5X clock manager to main PLL C0
Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19
|