Searched hist:"5 c6aa01affe14c40efdebdc9450cdbc4ae0bc494" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a76.h | 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 Mon Feb 25 15:17:44 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a76.S | 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 Mon Feb 25 15:17:44 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 Mon Feb 25 15:17:44 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|