Searched hist:"5 a45f0fca7002c2b5d4138d51d9ea5788440c229" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_x4.h | 5a45f0fca7002c2b5d4138d51d9ea5788440c229 Tue Jul 29 19:44:40 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X4 erratum 3887999
Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.
The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I851746b7b430eac85184c8d402d1aa5bb3c94a8e
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| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x4.S | 5a45f0fca7002c2b5d4138d51d9ea5788440c229 Tue Jul 29 19:44:40 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X4 erratum 3887999
Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.
The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I851746b7b430eac85184c8d402d1aa5bb3c94a8e
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 5a45f0fca7002c2b5d4138d51d9ea5788440c229 Tue Jul 29 19:44:40 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X4 erratum 3887999
Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.
The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I851746b7b430eac85184c8d402d1aa5bb3c94a8e
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 5a45f0fca7002c2b5d4138d51d9ea5788440c229 Tue Jul 29 19:44:40 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X4 erratum 3887999
Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.
The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I851746b7b430eac85184c8d402d1aa5bb3c94a8e
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