Searched hist:"50 bde47fe3f861a707d48cb36e556369a03f36f6" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/m0/src/ |
| H A D | dram.c | 50bde47fe3f861a707d48cb36e556369a03f36f6 Thu Feb 02 02:09:13 UTC 2017 Derek Basehore <dbasehore@chromium.org> rockchip: rk3399: Move DQS drive strength setting to M0
This moves the setting of the DQS drive strength to the M0 to minimize
the impact on DDR transactions. We need to have the DQS drive strength
changed for data training, which is triggered by the M0, but it also
needs to be changed back when data training is finished.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | dfs.c | 50bde47fe3f861a707d48cb36e556369a03f36f6 Thu Feb 02 02:09:13 UTC 2017 Derek Basehore <dbasehore@chromium.org> rockchip: rk3399: Move DQS drive strength setting to M0
This moves the setting of the DQS drive strength to the M0 to minimize
the impact on DDR transactions. We need to have the DQS drive strength
changed for data training, which is triggered by the M0, but it also
needs to be changed back when data training is finished.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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