Searched hist:"4 f9226b40379847339af8a7777be26f2db72e79b" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/mips/include/asm/ |
| H A D | mipsregs.h | 4f9226b40379847339af8a7777be26f2db72e79b Wed Sep 21 10:18:50 UTC 2016 Paul Burton <paul.burton@imgtec.com> MIPS: Preserve Config implementation-defined bits
The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS architecture.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
| /rk3399_rockchip-uboot/arch/mips/cpu/ |
| H A D | start.S | 4f9226b40379847339af8a7777be26f2db72e79b Wed Sep 21 10:18:50 UTC 2016 Paul Burton <paul.burton@imgtec.com> MIPS: Preserve Config implementation-defined bits
The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS architecture.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|