Home
last modified time | relevance | path

Searched hist:"4 bea194c62f52716b1096aaab7e80e8fead0cb9e" (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_pll.c4bea194c62f52716b1096aaab7e80e8fead0cb9e Fri Jun 25 07:06:38 UTC 2021 Joseph Chen <chenjh@rock-chips.com> clk: rockchip: pll: add lock timeout

It's more friendly for FPGA board.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8b6eb63ddf2b5c8742941e4e62444acba88feb31