Searched hist:"4 bd1d3faed7893e8e7d74f82b4b5de7443f434bd" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | dfs.h | 4bd1d3faed7893e8e7d74f82b4b5de7443f434bd Fri Feb 24 06:31:36 UTC 2017 Derek Basehore <dbasehore@chromium.org> rockchip: rk3399: add support for ddrfreq suspend/resume
This patch sets the frequency configuration of the next DRAM DFS index
to the configuration of the current index. This does not perform a
frequency transition. It just configures registers so the training on
resume for both indices will be correct.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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| H A D | suspend.c | 4bd1d3faed7893e8e7d74f82b4b5de7443f434bd Fri Feb 24 06:31:36 UTC 2017 Derek Basehore <dbasehore@chromium.org> rockchip: rk3399: add support for ddrfreq suspend/resume
This patch sets the frequency configuration of the next DRAM DFS index
to the configuration of the current index. This does not perform a
frequency transition. It just configures registers so the training on
resume for both indices will be correct.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
|
| H A D | dfs.c | 4bd1d3faed7893e8e7d74f82b4b5de7443f434bd Fri Feb 24 06:31:36 UTC 2017 Derek Basehore <dbasehore@chromium.org> rockchip: rk3399: add support for ddrfreq suspend/resume
This patch sets the frequency configuration of the next DRAM DFS index
to the configuration of the current index. This does not perform a
frequency transition. It just configures registers so the training on
resume for both indices will be correct.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
|
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/ |
| H A D | pmu.c | 4bd1d3faed7893e8e7d74f82b4b5de7443f434bd Fri Feb 24 06:31:36 UTC 2017 Derek Basehore <dbasehore@chromium.org> rockchip: rk3399: add support for ddrfreq suspend/resume
This patch sets the frequency configuration of the next DRAM DFS index
to the configuration of the current index. This does not perform a
frequency transition. It just configures registers so the training on
resume for both indices will be correct.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
|