Searched hist:"44 d50f0b54ef14534440bc5d789ec65240dfc0f8" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/board/freescale/p2041rdb/ |
| H A D | cpld.h | 44d50f0b54ef14534440bc5d789ec65240dfc0f8 Tue Sep 13 09:55:11 UTC 2011 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/p2041rdb: set sysclk according to status of physical switch SW1
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.
SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| H A D | p2041rdb.c | 44d50f0b54ef14534440bc5d789ec65240dfc0f8 Tue Sep 13 09:55:11 UTC 2011 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/p2041rdb: set sysclk according to status of physical switch SW1
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.
SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | P2041RDB.h | 44d50f0b54ef14534440bc5d789ec65240dfc0f8 Tue Sep 13 09:55:11 UTC 2011 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/p2041rdb: set sysclk according to status of physical switch SW1
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.
SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|