Searched hist:"40 ff90747098ed9d2a09894d1a886c10ca76cee6" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | el3_common_macros.S | 40ff90747098ed9d2a09894d1a886c10ca76cee6 Wed Jun 23 19:02:39 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(trbe): initialize trap settings of trace buffer control registers access
Trap bits of trace buffer control registers access are in
architecturally UNKNOWN state at boot hence
1. Initialized these bits to zero to prohibit trace buffer control
registers accesses in lower ELs (EL2, EL1) in all security states
when FEAT_TRBE is implemented
2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and
hence setting it to zero also aligns with the Arm ARM reference
recommendation, that mentions software must writes RES0 bits with
all 0s
Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|
| H A D | arch.h | 40ff90747098ed9d2a09894d1a886c10ca76cee6 Wed Jun 23 19:02:39 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(trbe): initialize trap settings of trace buffer control registers access
Trap bits of trace buffer control registers access are in
architecturally UNKNOWN state at boot hence
1. Initialized these bits to zero to prohibit trace buffer control
registers accesses in lower ELs (EL2, EL1) in all security states
when FEAT_TRBE is implemented
2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and
hence setting it to zero also aligns with the Arm ARM reference
recommendation, that mentions software must writes RES0 bits with
all 0s
Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context_mgmt.c | 40ff90747098ed9d2a09894d1a886c10ca76cee6 Wed Jun 23 19:02:39 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(trbe): initialize trap settings of trace buffer control registers access
Trap bits of trace buffer control registers access are in
architecturally UNKNOWN state at boot hence
1. Initialized these bits to zero to prohibit trace buffer control
registers accesses in lower ELs (EL2, EL1) in all security states
when FEAT_TRBE is implemented
2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and
hence setting it to zero also aligns with the Arm ARM reference
recommendation, that mentions software must writes RES0 bits with
all 0s
Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|