Searched hist:"3 c640c124ec02f3f0e6bbc5b6d364a0b851ba1ad" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | agilex5_cache.h | 3c640c124ec02f3f0e6bbc5b6d364a0b851ba1ad Fri May 31 10:40:22 UTC 2024 Tanmay Kathpalia <tanmay.kathpalia@intel.com> fix(intel): add cache invalidation during BL31 initialization
During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the sync-up of stale
values in the cache to be synced with the main memory.
So, before the cache cleaning is done in u-boot proper,
it is invalidated in BL31 so that the cache data gets in
sync with u-boot proper memory address space and when
u-boot proper does its initialization which in turn clears
its BSS and heap section.
Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_cache.S | 3c640c124ec02f3f0e6bbc5b6d364a0b851ba1ad Fri May 31 10:40:22 UTC 2024 Tanmay Kathpalia <tanmay.kathpalia@intel.com> fix(intel): add cache invalidation during BL31 initialization
During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the sync-up of stale
values in the cache to be synced with the main memory.
So, before the cache cleaning is done in u-boot proper,
it is invalidated in BL31 so that the cache data gets in
sync with u-boot proper memory address space and when
u-boot proper does its initialization which in turn clears
its BSS and heap section.
Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/ |
| H A D | platform.mk | 3c640c124ec02f3f0e6bbc5b6d364a0b851ba1ad Fri May 31 10:40:22 UTC 2024 Tanmay Kathpalia <tanmay.kathpalia@intel.com> fix(intel): add cache invalidation during BL31 initialization
During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the sync-up of stale
values in the cache to be synced with the main memory.
So, before the cache cleaning is done in u-boot proper,
it is invalidated in BL31 so that the cache data gets in
sync with u-boot proper memory address space and when
u-boot proper does its initialization which in turn clears
its BSS and heap section.
Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
|
| H A D | bl31_plat_setup.c | 3c640c124ec02f3f0e6bbc5b6d364a0b851ba1ad Fri May 31 10:40:22 UTC 2024 Tanmay Kathpalia <tanmay.kathpalia@intel.com> fix(intel): add cache invalidation during BL31 initialization
During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the sync-up of stale
values in the cache to be synced with the main memory.
So, before the cache cleaning is done in u-boot proper,
it is invalidated in BL31 so that the cache data gets in
sync with u-boot proper memory address space and when
u-boot proper does its initialization which in turn clears
its BSS and heap section.
Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
|