| #
f06fdb14 |
| 21-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): fix CCU for cache maintenance
Fix CCU settings for cache maintenance.
Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93 Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Signed-
fix(intel): fix CCU for cache maintenance
Fix CCU settings for cache maintenance.
Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93 Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
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| #
3c640c12 |
| 31-May-2024 |
Tanmay Kathpalia <tanmay.kathpalia@intel.com> |
fix(intel): add cache invalidation during BL31 initialization
During warm boot, the data cache is invalidated before enabling them in u-boot proper, this cache invalidation (+ cleaning) leads to the
fix(intel): add cache invalidation during BL31 initialization
During warm boot, the data cache is invalidated before enabling them in u-boot proper, this cache invalidation (+ cleaning) leads to the sync-up of stale values in the cache to be synced with the main memory. So, before the cache cleaning is done in u-boot proper, it is invalidated in BL31 so that the cache data gets in sync with u-boot proper memory address space and when u-boot proper does its initialization which in turn clears its BSS and heap section.
Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164 Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
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