| #
f3083e2e |
| 07-Aug-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): move common functions to common lib files" into integration
|
| #
6fcd047b |
| 07-Apr-2025 |
Jit Loon Lim <jit.loon.lim@altera.com> |
feat(intel): move common functions to common lib files
This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share a
feat(intel): move common functions to common lib files
This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share among files.
Change-Id: I19d9727eac895e7bf597a66076a7b68755cbe0ef
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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|
| #
5a162642 |
| 14-Mar-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): provide atf build version via smc call" into integration
|
| #
d1c58d86 |
| 02-Dec-2024 |
Girisha Dengi <girisha.dengi@intel.com> |
feat(intel): provide atf build version via smc call
This patch provides ATF build version via SMC call
on Agilex7, Agilex5, Stratix10 and N5X platforms.
Change-Id: I61af83433fe61f85987f38ffc86380a4
feat(intel): provide atf build version via smc call
This patch provides ATF build version via SMC call
on Agilex7, Agilex5, Stratix10 and N5X platforms.
Change-Id: I61af83433fe61f85987f38ffc86380a41cdb5289
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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|
| #
23828430 |
| 24-Feb-2025 |
Yann Gautier <yann.gautier@st.com> |
Merge "feat(intel): add FDT support for Altera products" into integration
|
| #
29d1e29d |
| 10-Feb-2025 |
Jit Loon Lim <jit.loon.lim@altera.com> |
feat(intel): add FDT support for Altera products
Support FDT for Agilex5 platform
1. Created wrapper file socfpga_dt.c
2. Added in Agilex5 dts file
3. Implemented fdt_check_header
4. Implemented gic
feat(intel): add FDT support for Altera products
Support FDT for Agilex5 platform
1. Created wrapper file socfpga_dt.c
2. Added in Agilex5 dts file
3. Implemented fdt_check_header
4. Implemented gic configuration
5. Implemented dram configuration
Remove init of FDT as Agilex5 has no plan to roll
out FDT at the moment.
Change-Id: If3990ed9524c6da5b3cb8966b63bc4a95d01fcda
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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|
| #
05b80761 |
| 28-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): add in JTAG ID for Linux FCS" into integration
|
| #
2c878eb6 |
| 28-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): add build option for boot source" into integration
|
| #
ea906b9b |
| 04-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): add in JTAG ID for Linux FCS
This is for SMMU and Remapper enabled/disabled for
Linux FCS feature. The JTAG ID is to determine which
Agilex5 model shall be implemented.
Change-Id: Ib10d
fix(intel): add in JTAG ID for Linux FCS
This is for SMMU and Remapper enabled/disabled for
Linux FCS feature. The JTAG ID is to determine which
Agilex5 model shall be implemented.
Change-Id: Ib10d0062de8f6e27413af3dd271d97b9c2e5c079
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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|
| #
ef8b05f5 |
| 24-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): add build option for boot source
Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update n
feat(intel): add build option for boot source
Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.
Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.
Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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|
| #
63446df6 |
| 16-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): update Agilex5 DDR and IOSSM driver" into integration
|
| #
ce21a1a9 |
| 26-Aug-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): update Agilex5 DDR and IOSSM driver
DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.
Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
feat(intel): update Agilex5 DDR and IOSSM driver
DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.
Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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|
| #
f17b7410 |
| 23-Sep-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): add cache invalidation during BL31 initialization" into integration
|
| #
3c640c12 |
| 31-May-2024 |
Tanmay Kathpalia <tanmay.kathpalia@intel.com> |
fix(intel): add cache invalidation during BL31 initialization
During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the
fix(intel): add cache invalidation during BL31 initialization
During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the sync-up of stale
values in the cache to be synced with the main memory.
So, before the cache cleaning is done in u-boot proper,
it is invalidated in BL31 so that the cache data gets in
sync with u-boot proper memory address space and when
u-boot proper does its initialization which in turn clears
its BSS and heap section.
Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
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|
| #
44c5f8e5 |
| 22-Aug-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge changes I23bdbbe1,Ic22ab741 into integration
* changes:
feat(intel): enable VAB support for Intel products
feat(intel): add in SHA384 authentication
|
| #
3eb5640a |
| 19-Jul-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): enable VAB support for Intel products
This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.
Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b
feat(intel): enable VAB support for Intel products
This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.
Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b3aff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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|
| #
51ff56e4 |
| 19-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(intel): enable SDMMC frontdoor load for ATF->Linux" into integration
|
| #
b3a7396d |
| 19-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes Iaa189c54,I8856b495 into integration
* changes:
feat(intel): enable query of fip offset on RSU
feat(intel): support query of fip offset using RSU
|
| #
6cbe2c5d |
| 22-Aug-2023 |
Mahesh Rao <mahesh.rao@intel.com> |
feat(intel): enable query of fip offset on RSU
Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform
Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Sign
feat(intel): enable query of fip offset on RSU
Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform
Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
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|
| #
9118bdf4 |
| 19-Dec-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration
|
| #
32a87d44 |
| 15-Oct-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): enable SDMMC frontdoor load for ATF->Linux
SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR f
feat(intel): enable SDMMC frontdoor load for ATF->Linux
SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR for Linux boot.
Change-Id: Ida303fb43ea63013a08083ce65952c5ad4e28f93
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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|
| #
150d2be0 |
| 07-Jul-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06a
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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|
| #
455cd0d3 |
| 19-Sep-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "chore: remove MULTI_CONSOLE_API references" into integration
|
| #
13ff6e9d |
| 12-Sep-2023 |
Michal Simek <michal.simek@amd.com> |
chore: remove MULTI_CONSOLE_API references
MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
reference
chore: remove MULTI_CONSOLE_API references
MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
references in platform.mk files and also in one rst which is not valid
anymore.
Change-Id: I45f8e7db0a14ce63de62509100d8159b7aca2657
Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
3393060c |
| 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
show more ...
|