Searched hist:"3 aed55074211b4e886d97f16773f186a019d508d" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/board/freescale/mpc8569mds/ |
| H A D | tlb.c | 3aed55074211b4e886d97f16773f186a019d508d Wed Sep 29 17:31:35 UTC 2010 Haiying Wang <Haiying.Wang@freescale.com> mpc8569mds: fix consuming long time while relocating code.
The original code maps boot flash as non-cacheable region. When calling
relocate_code in flash to copy u-boot from flash to ddr, every loop copy command
is read from flash. The flash read speed will be the bottleneck, which consuming
long time to do this operation. To resovle this, map the boot flash as
write-through cache via tlb. And set tlb to remap the flash after code
executing in ddr, to confirm flash erase operation properly done.
Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| H A D | mpc8569mds.c | 3aed55074211b4e886d97f16773f186a019d508d Wed Sep 29 17:31:35 UTC 2010 Haiying Wang <Haiying.Wang@freescale.com> mpc8569mds: fix consuming long time while relocating code.
The original code maps boot flash as non-cacheable region. When calling
relocate_code in flash to copy u-boot from flash to ddr, every loop copy command
is read from flash. The flash read speed will be the bottleneck, which consuming
long time to do this operation. To resovle this, map the boot flash as
write-through cache via tlb. And set tlb to remap the flash after code
executing in ddr, to confirm flash erase operation properly done.
Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | MPC8569MDS.h | 3aed55074211b4e886d97f16773f186a019d508d Wed Sep 29 17:31:35 UTC 2010 Haiying Wang <Haiying.Wang@freescale.com> mpc8569mds: fix consuming long time while relocating code.
The original code maps boot flash as non-cacheable region. When calling
relocate_code in flash to copy u-boot from flash to ddr, every loop copy command
is read from flash. The flash read speed will be the bottleneck, which consuming
long time to do this operation. To resovle this, map the boot flash as
write-through cache via tlb. And set tlb to remap the flash after code
executing in ddr, to confirm flash erase operation properly done.
Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|