Searched hist:"38636 fea416bf90b651a6623f94d2637282f9444" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/drivers/cadence/emmc/ |
| H A D | cdns_sdmmc.c | 38636fea416bf90b651a6623f94d2637282f9444 Tue Jul 01 11:16:46 UTC 2025 Boon Khai Ng <boon.khai.ng@altera.com> fix(intel): fix eMMC driver issues in boot flow on agilex5
Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correctly.
Added polling for the ICS bit after enabling ICE when
setting the SDCLK rate. Introduced delay to ensure
proper clock stabilization.
Corrected SD_HOST_CLK to data driven from the clock manager
as sdmclk.
eMMC operates in legacy mode, which has a maximum
supported clock rate of 26 MHz. Updated the clock
setting to 25 MHz to meet this requirement.
Change-Id: I4ac2b9b69b5dec2c8166d06c736d9c2c549607de
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/include/drivers/cadence/ |
| H A D | cdns_sdmmc.h | 38636fea416bf90b651a6623f94d2637282f9444 Tue Jul 01 11:16:46 UTC 2025 Boon Khai Ng <boon.khai.ng@altera.com> fix(intel): fix eMMC driver issues in boot flow on agilex5
Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correctly.
Added polling for the ICS bit after enabling ICE when
setting the SDCLK rate. Introduced delay to ensure
proper clock stabilization.
Corrected SD_HOST_CLK to data driven from the clock manager
as sdmclk.
eMMC operates in legacy mode, which has a maximum
supported clock rate of 26 MHz. Updated the clock
setting to 25 MHz to meet this requirement.
Change-Id: I4ac2b9b69b5dec2c8166d06c736d9c2c549607de
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|