Searched hist:"2 dc9fe70da6788ff69856ed247b10a59173431c3" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/fdts/ |
| H A D | stm32mp157a-dk1.dts | 2dc9fe70da6788ff69856ed247b10a59173431c3 Mon Jul 29 12:46:16 UTC 2019 Antonio Borneo <antonio.borneo@st.com> fdts: stm32mp1: move FDCAN to PLL4_R
LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.
This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.
Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58
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| H A D | stm32mp157a-avenger96.dts | 2dc9fe70da6788ff69856ed247b10a59173431c3 Mon Jul 29 12:46:16 UTC 2019 Antonio Borneo <antonio.borneo@st.com> fdts: stm32mp1: move FDCAN to PLL4_R
LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.
This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.
Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58
|
| H A D | stm32mp157c-ed1.dts | 2dc9fe70da6788ff69856ed247b10a59173431c3 Mon Jul 29 12:46:16 UTC 2019 Antonio Borneo <antonio.borneo@st.com> fdts: stm32mp1: move FDCAN to PLL4_R
LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.
This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.
Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58
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