Searched hist:"2831 bc3a5f5dd9cdd6f272044f9f916e68797ff1" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | suspend.h | 2831bc3a5f5dd9cdd6f272044f9f916e68797ff1 Wed Oct 26 17:13:16 UTC 2016 Caesar Wang <wxt@rock-chips.com> rockchip: add support save/restore configuration for DDR during enter S3
This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.
Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
|
| H A D | suspend.c | 2831bc3a5f5dd9cdd6f272044f9f916e68797ff1 Wed Oct 26 17:13:16 UTC 2016 Caesar Wang <wxt@rock-chips.com> rockchip: add support save/restore configuration for DDR during enter S3
This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.
Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
|
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/ |
| H A D | soc.h | 2831bc3a5f5dd9cdd6f272044f9f916e68797ff1 Wed Oct 26 17:13:16 UTC 2016 Caesar Wang <wxt@rock-chips.com> rockchip: add support save/restore configuration for DDR during enter S3
This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.
Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
|
| /rk3399_ARM-atf/plat/rockchip/rk3399/ |
| H A D | platform.mk | 2831bc3a5f5dd9cdd6f272044f9f916e68797ff1 Wed Oct 26 17:13:16 UTC 2016 Caesar Wang <wxt@rock-chips.com> rockchip: add support save/restore configuration for DDR during enter S3
This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.
Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
|