Searched hist:"2537 f0725ee7d8f46bef3e5b49134419b5c3367b" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/docs/plat/ |
| H A D | xilinx-zynqmp.rst | 2537f0725ee7d8f46bef3e5b49134419b5c3367b Wed Feb 15 05:19:52 UTC 2023 Akshay Belsare <akshay.belsare@amd.com> fix(zynqmp): with DEBUG=1 move bl31 to DDR range
Due to size constraints in OCM memory range keeping the bl31 with
DEBUG=1 overlaps with the memory range from other Firmware thus
affecting the bootflow on target.
bl31 binary can not be placed in OCM memory range when built with
DEBUG=1.
With DEBUG=1, by default bl31 is moved to DDR memory range
0x1000-0x7FFFF.
The user can provide a custom DDR memory range during build time using
the build parameters ZYNQMP_ATF_MEM_BASE and ZYNQMP_ATF_MEM_SIZE.
Change-Id: I167d5eadbae7c6d3ec9b32f494b0b1a819bea5b0
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/include/ |
| H A D | platform_def.h | 2537f0725ee7d8f46bef3e5b49134419b5c3367b Wed Feb 15 05:19:52 UTC 2023 Akshay Belsare <akshay.belsare@amd.com> fix(zynqmp): with DEBUG=1 move bl31 to DDR range
Due to size constraints in OCM memory range keeping the bl31 with
DEBUG=1 overlaps with the memory range from other Firmware thus
affecting the bootflow on target.
bl31 binary can not be placed in OCM memory range when built with
DEBUG=1.
With DEBUG=1, by default bl31 is moved to DDR memory range
0x1000-0x7FFFF.
The user can provide a custom DDR memory range during build time using
the build parameters ZYNQMP_ATF_MEM_BASE and ZYNQMP_ATF_MEM_SIZE.
Change-Id: I167d5eadbae7c6d3ec9b32f494b0b1a819bea5b0
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
|