Searched hist:"11 d5a629f8a40f9d7cffc74e58f4e3ed258e56ab" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/board/sbc8548/ |
| H A D | tlb.c | 11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab Mon Sep 21 00:36:04 UTC 2009 Paul Gortmaker <paul.gortmaker@windriver.com> sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| H A D | sbc8548.c | 11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab Mon Sep 21 00:36:04 UTC 2009 Paul Gortmaker <paul.gortmaker@windriver.com> sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | sbc8548.h | 11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab Mon Sep 21 00:36:04 UTC 2009 Paul Gortmaker <paul.gortmaker@windriver.com> sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|