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/OK3568_Linux_fs/buildroot/board/zynqmp/patches/uboot/
H A D0004-arm-arm64-zynq-zynqmp-pass-the-PS-init-file-as-a-kco.patch12 board/xilinx/zynq[mp]/$(CONFIG_DEFAULT_DEVICE_TREE)/ps?_init_gpl.c
14 2. otherwise use board/xilinx/zynq/ps?_init_gpl.c
18 build. This is typical when it is generated from Xilinx tools while
22 meta-xilinx yocto layer [0]).
48 non-existing), in-tree board-specific, in board/xilinx/zynq[mp]/
51 [0] https://github.com/Xilinx/meta-xilinx/blob/b2f74cc7fe5c4881589d5e440a17cb51fc66a7ab/meta-xilinx…
55 Cc: Michal Simek <michal.simek@xilinx.com>
60 board/xilinx/Kconfig | 41 +++++++++++++++++++++++++++++++++++++++++
61 board/xilinx/zynq/Makefile | 10 +++++++++-
62 board/xilinx/zynqmp/Makefile | 10 +++++++++-
[all …]
H A D0001-arm64-zynqmp-zcu106-fix-SPL-MMC-booting.patch21 https://github.com/xilinx/hdf-examples/tree/01ad8ea5fd1989abf4ea5a072d019a16cb2bc546/zcu106-zynqmp
30 Cc: Michal Simek <michal.simek@xilinx.com>
34 board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 2 +-
37 diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu…
39 --- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
40 +++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/
H A Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
89 That covers the general approach to binding xilinx IP cores into the
92 i) Xilinx ML300 Framebuffer
105 ii) Xilinx SystemACE
107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
114 iii) Xilinx EMAC and Xilinx TEMAC
116 Xilinx Ethernet devices. In addition to general xilinx properties
121 iv) Xilinx Uartlite
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dxilinx.yaml4 $id: http://devicetree.org/schemas/arm/xilinx.yaml#
7 title: Xilinx Zynq Platforms Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
49 - description: Xilinx internal board zc1232
55 - description: Xilinx internal board zc1254
61 - description: Xilinx internal board zc1275
67 - description: Xilinx 96boards compatible board zcu100
73 - description: Xilinx 96boards compatible board Ultra96
81 - description: Xilinx evaluation board zcu102
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/xilinx/
H A DKconfig7 bool "Xilinx devices"
14 the questions about Xilinx devices. If you say Y, you will be asked
20 tristate "Xilinx 10/100 Ethernet Lite support"
24 This driver supports the 10/100 Ethernet Lite from Xilinx.
27 tristate "Xilinx 10/100/1000 AXI Ethernet support"
30 This driver supports the 10/100/1000 Ethernet from Xilinx for the
31 AXI bus interface used in Xilinx Virtex FPGAs and Soc's.
34 tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
37 This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
38 core used in Xilinx Spartan and Virtex FPGAs
/OK3568_Linux_fs/kernel/drivers/media/platform/xilinx/
H A DMakefile3 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
5 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
6 obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
7 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
8 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
H A DKconfig4 tristate "Xilinx Video IP (EXPERIMENTAL)"
11 Driver for Xilinx Video IP Pipelines
16 tristate "Xilinx CSI-2 Rx Subsystem"
18 Driver for Xilinx MIPI CSI-2 Rx Subsystem. This is a V4L sub-device
23 tristate "Xilinx Video Test Pattern Generator"
27 Driver for the Xilinx Video Test Pattern Generator
30 tristate "Xilinx Video Timing Controller"
33 Driver for the Xilinx Video Timing Controller
/OK3568_Linux_fs/buildroot/board/zynq/
H A Dreadme.txt2 Xilinx and some third party vendors, but the build procedure is very similar.
5 - Xilinx ZC706 board (zynq_zc706_defconfig)
37 https://forums.xilinx.com/t5/Embedded-Linux/Microzed-default-device-tree-dts/td-p/432856.
42 http://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html.
62 output from the Xilinx tools, but for convenience, U-Boot includes the
66 board/xilinx/zynq/ directory of U-Boot for natively supported ps7_init
77 [*] Use custom ps7_init provided by Xilinx tool
79 3) Copy ps7_init_gpl.c/h generated by the Xilinx tools into
80 output/build/uboot-xilinx-<pkg version>/board/xilinx/zynq/custom_hw_platform/
/OK3568_Linux_fs/kernel/sound/soc/xilinx/
H A DKconfig3 tristate "Audio support for the Xilinx I2S"
5 Select this option to enable Xilinx I2S Audio. This enables
6 I2S playback and capture using xilinx soft IP. In transmitter
12 tristate "Audio support for the Xilinx audio formatter"
14 Select this option to enable Xilinx audio formatter
19 tristate "Audio support for the Xilinx SPDIF"
21 Select this option to enable Xilinx SPDIF Audio.
/OK3568_Linux_fs/kernel/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp4 Contact: "Jolly Shah" <jollys@xilinx.com>
13 other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}.
25 Users: Xilinx
30 Contact: "Jolly Shah" <jollys@xilinx.com>
40 Four registers are used by the FSBL and other Xilinx
54 Users: Xilinx
59 Contact: "Jolly Shah" <jollys@xilinx.com>
91 Users: Xilinx
96 Contact: "Jolly Shah" <jollys@xilinx.com>
115 Users: Xilinx
/OK3568_Linux_fs/kernel/drivers/irqchip/
H A Dirq-xilinx-intc.c3 * Copyright (C) 2012-2013 Xilinx, Inc.
67 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); in intc_enable_or_unmask()
83 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); in intc_disable_or_mask()
91 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); in intc_ack()
100 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); in intc_mask_ack()
106 .name = "Xilinx INTC",
122 pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); in xintc_get_irq_local()
136 pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); in xintc_get_irq()
194 pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); in xilinx_intc_of_init()
200 pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n"); in xilinx_intc_of_init()
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.zynq2 # Xilinx ZYNQ U-Boot
4 # (C) Copyright 2013 Xilinx, Inc.
11 This document describes the information about Xilinx Zynq U-Boot -
16 Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
80 [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
81 [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
84 [5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
87 Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
/OK3568_Linux_fs/buildroot/board/qemu/microblazeel-mmu/
H A D0001-net-xilinx-xemaclite-add-2.00.b-revision.patch4 Subject: [PATCH] net: xilinx: xemaclite: add 2.00.b revision
11 https://git.buildroot.net/buildroot/commit/board/qemu/microblazebe-mmu/xilinx-xemaclite.patch?id=fa…
17 drivers/net/ethernet/xilinx/xilinx_emaclite.c | 1 +
20 diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_ema…
22 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
23 +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
/OK3568_Linux_fs/buildroot/board/qemu/microblazebe-mmu/
H A D0001-net-xilinx-xemaclite-add-2.00.b-revision.patch4 Subject: [PATCH] net: xilinx: xemaclite: add 2.00.b revision
11 https://git.buildroot.net/buildroot/commit/board/qemu/microblazebe-mmu/xilinx-xemaclite.patch?id=fa…
17 drivers/net/ethernet/xilinx/xilinx_emaclite.c | 1 +
20 diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_ema…
22 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
23 +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
/OK3568_Linux_fs/kernel/drivers/net/ethernet/sfc/
H A Def100.c5 * Copyright 2019-2020 Xilinx Inc.
32 /* Expected size of a Xilinx continuation address table entry. */
86 "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n", in ef100_pci_parse_ef100_entry()
104 /* Parse a Xilinx capabilities table entry describing a continuation to a new
128 "Bad BAR value of %d in Xilinx capabilities sub-table.\n", in ef100_pci_parse_continue_entry()
138 "Xilinx table will overrun BAR[%d] offset=0x%llx\n", in ef100_pci_parse_continue_entry()
149 "Mapping new BAR for Xilinx table failed, rc=%d\n", rc); in ef100_pci_parse_continue_entry()
175 /* Iterate over the Xilinx capabilities table in the currently mapped BAR and
197 "Seen Xilinx table entry 0x%x size 0x%x at 0x%llx in BAR[%d]\n", in ef100_pci_walk_xilinx_table()
202 "Xilinx table entry too short len=0x%x\n", entry_size); in ef100_pci_walk_xilinx_table()
[all …]
/OK3568_Linux_fs/kernel/arch/microblaze/pci/
H A Dxilinx_pci.c2 * PCI support for Xilinx plbv46_pci soft-core which can be used on
3 * Xilinx Virtex ML410 / ML510 boards.
36 * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
62 dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n", in xilinx_pci_fixup_bridge()
120 * xilinx_pci_init - Find and register a Xilinx PCI host bridge
134 pr_err("xilinx-pci: cannot resolve base address\n"); in xilinx_pci_init()
140 pr_err("xilinx-pci: pcibios_alloc_controller() failed\n"); in xilinx_pci_init()
149 /* According to the xilinx plbv46_pci documentation the soft-core starts in xilinx_pci_init()
168 pr_info("xilinx-pci: Registered PCI host bridge\n"); in xilinx_pci_init()
/OK3568_Linux_fs/kernel/drivers/staging/gs_fpgaboot/
H A DREADME2 Linux Driver Source for Xilinx FPGA firmware download
16 - Download Xilinx FPGA firmware
17 - This module downloads Xilinx FPGA firmware using gpio pins.
28 - load Xilinx FPGA bitstream format[1] firmware image file using
30 - program the Xilinx FPGA using SelectMAP (parallel) mode [2]
67 1. Xilinx APP NOTE XAPP583:
68 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
/OK3568_Linux_fs/kernel/sound/pci/mixart/
H A Dmixart_hwdep.c338 /* read motherboard xilinx status */ in mixart_dsp_load()
342 /* read daughterboard xilinx status */ in mixart_dsp_load()
345 /* motherboard xilinx status 5 will say that the board is performing a reset */ in mixart_dsp_load()
354 /* xilinx already loaded ? */ in mixart_dsp_load()
356 dev_dbg(&mgr->pci->dev, "xilinx is already loaded !\n"); in mixart_dsp_load()
362 "xilinx load error ! status = %d\n", in mixart_dsp_load()
367 /* check xilinx validity */ in mixart_dsp_load()
373 /* set xilinx status to copying */ in mixart_dsp_load()
376 /* setup xilinx base address */ in mixart_dsp_load()
378 /* setup code size for xilinx file */ in mixart_dsp_load()
[all …]
/OK3568_Linux_fs/kernel/drivers/firmware/xilinx/
H A Dzynqmp-debug.h3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2018 Xilinx
7 * Michal Simek <michal.simek@xilinx.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
/OK3568_Linux_fs/buildroot/configs/
H A Dzynq_zc706_defconfig10 …_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xilinx-v2017.3)/linux-xilin…
22 BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/Xilinx/u-boot-xlnx.git"
23 BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="xilinx-v2018.2"
H A Dzynq_microzed_defconfig10 …_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xilinx-v2017.3)/linux-xilin…
22 BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/Xilinx/u-boot-xlnx.git"
23 BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="xilinx-v2018.2"
H A Dzynq_qmtech_defconfig11 …LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xilinx-v2019.2.01)/linux-xil…
23 …STOM_TARBALL_LOCATION="$(call github,jolivain,u-boot-xlnx,xilinx-v2019.2.qmtech.1)/uboot-xilinx-v2…
/OK3568_Linux_fs/kernel/drivers/fpga/
H A DKconfig56 tristate "Xilinx Zynq FPGA"
59 FPGA manager driver support for Xilinx Zynq FPGAs.
68 tristate "Xilinx Configuration over Slave Serial (SPI)"
71 FPGA manager driver support for Xilinx FPGA configuration
117 tristate "Xilinx LogiCORE PR Decoupler"
121 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
211 tristate "Xilinx ZynqMP FPGA"
214 FPGA manager driver support for Xilinx ZynqMP FPGAs.
/OK3568_Linux_fs/kernel/drivers/char/xilinx_hwicap/
H A Dfifo_icap.h3 * Author: Xilinx, Inc.
10 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
12 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
14 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
17 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
24 * (c) Copyright 2007-2008 Xilinx Inc.
H A Dbuffer_icap.h3 * Author: Xilinx, Inc.
10 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
12 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
14 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
17 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
24 * (c) Copyright 2003-2008 Xilinx Inc.

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