Searched +full:r7s72100 +full:- +full:ports (Results 1 – 10 of 10) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Jacopo Mondi <jacopo+renesas@jmondi.org>11 - Geert Uytterhoeven <geert+renesas@glider.be>15 controller, named "Ports" in the hardware reference manual.16 Pin multiplexing and GPIO configuration is performed on a per-pin basis17 writing configuration values to per-port register sets.25 - const: renesas,r7s72100-ports # RZ/A1H[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the r7s72100 SoC5 * Copyright (C) 2013-14 Renesas Solutions Corp.6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>9 #include <dt-bindings/clock/r7s72100-clock.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/interrupt-controller/irq.h>14 compatible = "renesas,r7s72100";15 #address-cells = <1>;16 #size-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the GR-Peach board9 /dts-v1/;10 #include "r7s72100.dtsi"11 #include <dt-bindings/gpio/gpio.h>12 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>15 model = "GR-Peach";16 compatible = "renesas,gr-peach", "renesas,r7s72100";24 stdout-path = "serial0:115200n8";33 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2013-14 Renesas Solutions Corp.6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>9 /dts-v1/;10 #include "r7s72100.dtsi"11 #include <dt-bindings/gpio/gpio.h>12 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>16 compatible = "renesas,genmai", "renesas,r7s72100";24 stdout-path = "serial0:115200n8";33 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.08 /dts-v1/;9 #include "r7s72100.dtsi"10 #include <dt-bindings/gpio/gpio.h>11 #include <dt-bindings/input/input.h>12 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>16 compatible = "renesas,rskrza1", "renesas,r7s72100";24 stdout-path = "serial0:115200n8";33 compatible = "gpio-keys";35 pinctrl-names = "default";[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC11 * This includes SoCs which are sub- or super- sets of this particular line,24 #include <linux/pinctrl/pinconf-generic.h>34 #define DRIVER_NAME "pinctrl-rza1"74 /* ----------------------------------------------------------------------------79 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.87 * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.96 * rza1_swio_pin - describe a single pin that needs swio flag applied.106 * rza1_swio_entry - describe a list of pins that needs swio flag applied[all …]
1 # SPDX-License-Identifier: GPL-2.044 once the kernel has booted up - it's a one time check.96 1 - undefined instruction events97 2 - system calls98 4 - invalid data aborts99 8 - SIGSEGV faults100 16 - SIGBUS faults104 bool "Kernel low-level debugging functions (read help!)"117 prompt "Kernel low-level debugging port"121 bool "Kernel low-level debugging messages via Alpine UART0"[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu6 * Copyright (C) 2008-2014 Renesas Solutions Corp.7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.15 #include <linux/dma-mapping.h>19 #include <linux/mdio-bitbang.h>46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID55 __diag_ignore(GCC, 8, "-Woverride-init",352 u16 offset = mdp->reg_offset[enum_index]; in sh_eth_write()357 iowrite32(data, mdp->addr + offset); in sh_eth_write()[all …]
1 // SPDX-License-Identifier: GPL-2.03 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)5 * Copyright (C) 2002 - 2011 Paul Mundt9 * based off of the old drivers/char/sh-sci.c by:13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).26 #include <linux/dma-mapping.h>57 #include "sh-sci.h"59 /* Offsets into the sci_port->irqs array */73 ((port)->irqs[SCIx_ERI_IRQ] == \74 (port)->irqs[SCIx_RXI_IRQ]) || \[all …]
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