1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the RZ/A1H RSK board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Renesas Electronics 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun#include "r7s72100.dtsi" 10*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 11*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 12*4882a593Smuzhiyun#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "RSKRZA1"; 16*4882a593Smuzhiyun compatible = "renesas,rskrza1", "renesas,r7s72100"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun aliases { 19*4882a593Smuzhiyun serial0 = &scif2; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun chosen { 23*4882a593Smuzhiyun bootargs = "ignore_loglevel"; 24*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun memory@8000000 { 28*4882a593Smuzhiyun device_type = "memory"; 29*4882a593Smuzhiyun reg = <0x08000000 0x02000000>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun keyboard { 33*4882a593Smuzhiyun compatible = "gpio-keys"; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun pinctrl-names = "default"; 36*4882a593Smuzhiyun pinctrl-0 = <&keyboard_pins>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun key-1 { 39*4882a593Smuzhiyun interrupt-parent = <&irqc>; 40*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_EDGE_BOTH>; 41*4882a593Smuzhiyun linux,code = <KEY_1>; 42*4882a593Smuzhiyun label = "SW1"; 43*4882a593Smuzhiyun wakeup-source; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun key-2 { 47*4882a593Smuzhiyun interrupt-parent = <&irqc>; 48*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_EDGE_BOTH>; 49*4882a593Smuzhiyun linux,code = <KEY_2>; 50*4882a593Smuzhiyun label = "SW2"; 51*4882a593Smuzhiyun wakeup-source; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun key-3 { 55*4882a593Smuzhiyun interrupt-parent = <&irqc>; 56*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_EDGE_BOTH>; 57*4882a593Smuzhiyun linux,code = <KEY_3>; 58*4882a593Smuzhiyun label = "SW3"; 59*4882a593Smuzhiyun wakeup-source; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun lbsc { 64*4882a593Smuzhiyun #address-cells = <1>; 65*4882a593Smuzhiyun #size-cells = <1>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun leds { 69*4882a593Smuzhiyun compatible = "gpio-leds"; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun led0 { 72*4882a593Smuzhiyun gpios = <&port7 1 GPIO_ACTIVE_LOW>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun led1 { 76*4882a593Smuzhiyun gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun led2 { 80*4882a593Smuzhiyun gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun led3 { 84*4882a593Smuzhiyun gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&extal_clk { 90*4882a593Smuzhiyun clock-frequency = <13330000>; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&i2c3 { 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&i2c3_pins>; 96*4882a593Smuzhiyun status = "okay"; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun clock-frequency = <400000>; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun io_expander1: gpio@20 { 101*4882a593Smuzhiyun compatible = "onnn,cat9554"; 102*4882a593Smuzhiyun reg = <0x20>; 103*4882a593Smuzhiyun gpio-controller; 104*4882a593Smuzhiyun #gpio-cells = <2>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun io_expander2: gpio@21 { 108*4882a593Smuzhiyun compatible = "onnn,cat9554"; 109*4882a593Smuzhiyun reg = <0x21>; 110*4882a593Smuzhiyun gpio-controller; 111*4882a593Smuzhiyun #gpio-cells = <2>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun eeprom@50 { 115*4882a593Smuzhiyun compatible = "renesas,r1ex24016", "atmel,24c16"; 116*4882a593Smuzhiyun reg = <0x50>; 117*4882a593Smuzhiyun pagesize = <16>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&usb_x1_clk { 122*4882a593Smuzhiyun clock-frequency = <48000000>; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&rtc_x1_clk { 126*4882a593Smuzhiyun clock-frequency = <32768>; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun&pinctrl { 130*4882a593Smuzhiyun /* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */ 131*4882a593Smuzhiyun i2c3_pins: i2c3 { 132*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(1, 6, 1)>, /* RIIC3SCL */ 133*4882a593Smuzhiyun <RZA1_PINMUX(1, 7, 1)>; /* RIIC3SDA */ 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun keyboard_pins: keyboard { 137*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(1, 9, 3)>, /* IRQ3 */ 138*4882a593Smuzhiyun <RZA1_PINMUX(1, 8, 3)>, /* IRQ2 */ 139*4882a593Smuzhiyun <RZA1_PINMUX(1, 11, 3)>; /* IRQ5 */ 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* Serial Console */ 143*4882a593Smuzhiyun scif2_pins: serial2 { 144*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */ 145*4882a593Smuzhiyun <RZA1_PINMUX(3, 2, 4)>; /* RxD2 */ 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* Ethernet */ 149*4882a593Smuzhiyun ether_pins: ether { 150*4882a593Smuzhiyun /* Ethernet on Ports 1,2,3,5 */ 151*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */ 152*4882a593Smuzhiyun <RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */ 153*4882a593Smuzhiyun <RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */ 154*4882a593Smuzhiyun <RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */ 155*4882a593Smuzhiyun <RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */ 156*4882a593Smuzhiyun <RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */ 157*4882a593Smuzhiyun <RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */ 158*4882a593Smuzhiyun <RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */ 159*4882a593Smuzhiyun <RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */ 160*4882a593Smuzhiyun <RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */ 161*4882a593Smuzhiyun <RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */ 162*4882a593Smuzhiyun <RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */ 163*4882a593Smuzhiyun <RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */ 164*4882a593Smuzhiyun <RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */ 165*4882a593Smuzhiyun <RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */ 166*4882a593Smuzhiyun <RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */ 167*4882a593Smuzhiyun <RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */ 168*4882a593Smuzhiyun <RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */ 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* SDHI ch1 on CN1 */ 172*4882a593Smuzhiyun sdhi1_pins: sdhi1 { 173*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */ 174*4882a593Smuzhiyun <RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */ 175*4882a593Smuzhiyun <RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */ 176*4882a593Smuzhiyun <RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */ 177*4882a593Smuzhiyun <RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */ 178*4882a593Smuzhiyun <RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */ 179*4882a593Smuzhiyun <RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */ 180*4882a593Smuzhiyun <RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */ 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun}; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun&mtu2 { 185*4882a593Smuzhiyun status = "okay"; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyunðer { 189*4882a593Smuzhiyun pinctrl-names = "default"; 190*4882a593Smuzhiyun pinctrl-0 = <ðer_pins>; 191*4882a593Smuzhiyun status = "okay"; 192*4882a593Smuzhiyun renesas,no-ether-link; 193*4882a593Smuzhiyun phy-handle = <&phy0>; 194*4882a593Smuzhiyun phy0: ethernet-phy@0 { 195*4882a593Smuzhiyun reg = <0>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun}; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun&sdhi1 { 200*4882a593Smuzhiyun pinctrl-names = "default"; 201*4882a593Smuzhiyun pinctrl-0 = <&sdhi1_pins>; 202*4882a593Smuzhiyun bus-width = <4>; 203*4882a593Smuzhiyun status = "okay"; 204*4882a593Smuzhiyun}; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun&ostm0 { 207*4882a593Smuzhiyun status = "okay"; 208*4882a593Smuzhiyun}; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun&ostm1 { 211*4882a593Smuzhiyun status = "okay"; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun&rtc { 215*4882a593Smuzhiyun status = "okay"; 216*4882a593Smuzhiyun}; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun&scif2 { 219*4882a593Smuzhiyun pinctrl-names = "default"; 220*4882a593Smuzhiyun pinctrl-0 = <&scif2_pins>; 221*4882a593Smuzhiyun status = "okay"; 222*4882a593Smuzhiyun}; 223