Searched full:pllc0 (Results 1 – 4 of 4) sorted by relevance
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | renesas,cpg-clocks.yaml | 106 - const: pllc0
237 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
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| /OK3568_Linux_fs/kernel/drivers/clk/renesas/ |
| H A D | clk-r8a7740.c | 93 } else if (!strcmp(name, "pllc0")) { in r8a7740_cpg_register_clock()
94 /* PLLC0/1 are configurable multiplier clocks. Register them as in r8a7740_cpg_register_clock()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/include/mach/ |
| H A D | hardware.h | 432 * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | r8a7740.dtsi | 484 clock-output-names = "system", "pllc0", "pllc1",
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