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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/i2c/
H A Dcdns,i2c-r1p10.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence I2C controller Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - cdns,i2c-r1p10 # cadence i2c controller version 1.0
19 - cdns,i2c-r1p14 # cadence i2c controller version 1.4
30 clock-frequency:
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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/i2c/
H A Di2c-cdns.txt1 Cadence I2C controller Device Tree Bindings
2 -------------------------------------------
5 - compatible : Should be "cdns,i2c-r1p10" or "xlnx,zynq-spi-r1p10".
6 - reg : Physical base address and size of I2C registers map.
7 - interrupts : Property with a value describing the interrupt
9 - interrupt-parent : Must be core interrupt controller
10 - clocks : Clock phandles (see clock bindings for details).
13 i2c0: i2c@e0004000 {
14 compatible = "cdns,i2c-r1p10";
18 interrupt-parent = <&intc>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi3 * Describes the hardware common to all Zynq 7000-based boards.
5 * Copyright (C) 2011 - 2015 Xilinx
7 * SPDX-License-Identifier: GPL-2.0+
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "xlnx,zynq-7000";
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
24 clock-latency = <1000>;
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H A Dzynqmp.dtsi4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "psci";
25 cpu-idle-states = <&CPU_SLEEP_0>;
29 compatible = "arm,cortex-a53", "arm,armv8";
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/OK3568_Linux_fs/u-boot/drivers/i2c/
H A Di2c-cdns.c3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 * This file is based on: drivers/i2c/zynq_i2c.c,
6 * with added driver-model support and code cleanup.
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <i2c.h>
24 /* i2c register set */
71 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
80 int_status = readl(&cdns_i2c->interrupt_status); in cdns_i2c_debug_status()
82 status = readl(&cdns_i2c->status); in cdns_i2c_debug_status()
111 debug("TS%d ", readl(&cdns_i2c->transfer_size)); in cdns_i2c_debug_status()
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/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for the Cadence I2C controller.
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/i2c.h>
18 /* Register offsets for the I2C device. */
21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
57 * I2C Address Register Bit mask definitions
59 * bits. A write access to this register always initiates a transfer if the I2C
62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
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/OK3568_Linux_fs/kernel/
H A DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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