Lines Matching +full:i2c +full:- +full:r1p10
3 * Describes the hardware common to all Zynq 7000-based boards.
5 * Copyright (C) 2011 - 2015 Xilinx
7 * SPDX-License-Identifier: GPL-2.0+
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "xlnx,zynq-7000";
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
24 clock-latency = <1000>;
25 cpu0-supply = <®ulator_vccpint>;
26 operating-points = <
34 compatible = "arm,cortex-a9";
41 fpga_full: fpga-full {
42 compatible = "fpga-region";
43 fpga-mgr = <&devcfg>;
44 #address-cells = <1>;
45 #size-cells = <1>;
50 compatible = "arm,cortex-a9-pmu";
52 interrupt-parent = <&intc>;
57 compatible = "regulator-fixed";
58 regulator-name = "VCCPINT";
59 regulator-min-microvolt = <1000000>;
60 regulator-max-microvolt = <1000000>;
61 regulator-boot-on;
62 regulator-always-on;
66 u-boot,dm-pre-reloc;
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 interrupt-parent = <&intc>;
74 compatible = "xlnx,zynq-xadc-1.00.a";
77 interrupt-parent = <&intc>;
82 compatible = "xlnx,zynq-can-1.0";
85 clock-names = "can_clk", "pclk";
88 interrupt-parent = <&intc>;
89 tx-fifo-depth = <0x40>;
90 rx-fifo-depth = <0x40>;
94 compatible = "xlnx,zynq-can-1.0";
97 clock-names = "can_clk", "pclk";
100 interrupt-parent = <&intc>;
101 tx-fifo-depth = <0x40>;
102 rx-fifo-depth = <0x40>;
106 compatible = "xlnx,zynq-gpio-1.0";
107 #gpio-cells = <2>;
108 #interrupt-cells = <2>;
110 gpio-controller;
111 interrupt-controller;
112 interrupt-parent = <&intc>;
117 i2c0: i2c@e0004000 {
118 compatible = "cdns,i2c-r1p10";
121 interrupt-parent = <&intc>;
124 #address-cells = <1>;
125 #size-cells = <0>;
128 i2c1: i2c@e0005000 {
129 compatible = "cdns,i2c-r1p10";
132 interrupt-parent = <&intc>;
135 #address-cells = <1>;
136 #size-cells = <0>;
139 intc: interrupt-controller@f8f01000 {
140 compatible = "arm,cortex-a9-gic";
141 #interrupt-cells = <3>;
142 interrupt-controller;
147 L2: cache-controller@f8f02000 {
148 compatible = "arm,pl310-cache";
151 arm,data-latency = <3 2 2>;
152 arm,tag-latency = <2 2 2>;
153 cache-unified;
154 cache-level = <2>;
157 mc: memory-controller@f8006000 {
158 compatible = "xlnx,zynq-ddrc-a05";
163 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
166 clock-names = "uart_clk", "pclk";
172 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
175 clock-names = "uart_clk", "pclk";
181 compatible = "xlnx,zynq-spi-r1p6";
184 interrupt-parent = <&intc>;
187 clock-names = "ref_clk", "pclk";
188 #address-cells = <1>;
189 #size-cells = <0>;
193 compatible = "xlnx,zynq-spi-r1p6";
196 interrupt-parent = <&intc>;
199 clock-names = "ref_clk", "pclk";
200 #address-cells = <1>;
201 #size-cells = <0>;
205 clock-names = "ref_clk", "pclk";
207 compatible = "xlnx,zynq-qspi-1.0";
209 interrupt-parent = <&intc>;
212 #address-cells = <1>;
213 #size-cells = <0>;
217 compatible = "cdns,zynq-gem", "cdns,gem";
222 clock-names = "pclk", "hclk", "tx_clk";
223 #address-cells = <1>;
224 #size-cells = <0>;
228 compatible = "cdns,zynq-gem", "cdns,gem";
233 clock-names = "pclk", "hclk", "tx_clk";
234 #address-cells = <1>;
235 #size-cells = <0>;
239 compatible = "arasan,sdhci-8.9a";
241 clock-names = "clk_xin", "clk_ahb";
243 interrupt-parent = <&intc>;
249 compatible = "arasan,sdhci-8.9a";
251 clock-names = "clk_xin", "clk_ahb";
253 interrupt-parent = <&intc>;
259 u-boot,dm-pre-reloc;
260 #address-cells = <1>;
261 #size-cells = <1>;
262 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
266 u-boot,dm-pre-reloc;
267 #clock-cells = <1>;
268 compatible = "xlnx,ps7-clkc";
269 fclk-enable = <0>;
270 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
285 compatible = "xlnx,zynq-reset";
287 #reset-cells = <1>;
292 compatible = "xlnx,pinctrl-zynq";
301 interrupt-parent = <&intc>;
302 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
309 #dma-cells = <1>;
310 #dma-channels = <8>;
311 #dma-requests = <4>;
313 clock-names = "apb_pclk";
317 compatible = "xlnx,zynq-devcfg-1.0";
318 interrupt-parent = <&intc>;
322 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
327 compatible = "arm,cortex-a9-global-timer";
330 interrupt-parent = <&intc>;
335 interrupt-parent = <&intc>;
343 interrupt-parent = <&intc>;
351 interrupt-parent = <&intc>;
353 compatible = "arm,cortex-a9-twd-timer";
359 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
362 interrupt-parent = <&intc>;
369 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
372 interrupt-parent = <&intc>;
380 compatible = "cdns,wdt-r1p2";
381 interrupt-parent = <&intc>;
384 timeout-sec = <10>;