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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/edac/
H A Dsocfpga-eccmgr.txt1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/
H A Dmtk_ecc.c3 * MTK ECC controller driver.
68 /* ecc strength that each IP supports */
119 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
122 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
126 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
136 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
139 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
142 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
143 if (dec & ecc->sectors) { in mtk_ecc_irq()
148 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); in mtk_ecc_irq()
[all …]
H A Domap2.c122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
170 /* fields specific for BCHx_HW ECC scheme */
718 * gen_true_ecc - This function will generate true ECC value
719 * @ecc_buf: buffer to store ecc code
721 * This generated true ECC value can be used when correcting
739 * @ecc_data1: ecc code from nand spare area
740 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
743 * This function compares two ECC's and indicates if there is an error.
819 * ECC values are equal in omap_compare_ecc()
[all …]
H A Dnand_micron.c15 * corrected by on-die ECC and should be rewritten.
20 * On chips with 8-bit ECC and additional bit can be used to distinguish
66 struct micron_on_die_ecc ecc; member
127 .ecc = micron_nand_on_die_4_ooblayout_ecc,
140 oobregion->offset = mtd->oobsize - chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
141 oobregion->length = chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
156 oobregion->length = mtd->oobsize - chip->ecc.total - 2; in micron_nand_on_die_8_ooblayout_free()
162 .ecc = micron_nand_on_die_8_ooblayout_ecc,
172 if (micron->ecc.forced) in micron_nand_on_die_ecc_setup()
175 if (micron->ecc.enabled == enable) in micron_nand_on_die_ecc_setup()
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H A Dnand_bch.c3 * This file provides ECC correction for more than 1 bit per block of data,
23 * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
32 * nand_bch_calculate_ecc - [NAND Interface] Calculate ECC for data block
35 * @code: output buffer with ECC
40 struct nand_bch_control *nbc = chip->ecc.priv; in nand_bch_calculate_ecc()
43 memset(code, 0, chip->ecc.bytes); in nand_bch_calculate_ecc()
44 bch_encode(nbc->bch, buf, chip->ecc.size, code); in nand_bch_calculate_ecc()
47 for (i = 0; i < chip->ecc.bytes; i++) in nand_bch_calculate_ecc()
58 * @read_ecc: ECC from the chip
59 * @calc_ecc: the ECC calculated from raw data
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H A Dnand_base.c22 * if we have HW ECC support.
262 res = chip->ecc.read_oob(chip, first_page + page_offset); in nand_block_bad()
433 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); in nand_do_write_oob()
435 status = chip->ecc.write_oob(chip, page & chip->pagemask); in nand_do_write_oob()
2496 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
2500 * @ecc: ECC buffer
2501 * @ecclen: ECC length
2506 * Check if a data buffer and its associated ECC and OOB data contains only
2513 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
2514 * different from the NAND page size. When fixing bitflips, ECC engines will
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/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/ingenic/
H A Dingenic_ecc.c3 * JZ47xx ECC common code
18 * ingenic_ecc_calculate() - calculate ECC for a data buffer
19 * @ecc: ECC device.
20 * @params: ECC parameters.
22 * @ecc_code: output buffer with ECC.
24 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
27 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
31 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
36 * @ecc: ECC device.
37 * @params: ECC parameters.
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H A Dingenic_nand_drv.c44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
90 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_free() local
95 oobregion->length = mtd->oobsize - ecc->total - 12; in qi_lb60_ooblayout_free()
96 oobregion->offset = 12 + ecc->total; in qi_lb60_ooblayout_free()
102 .ecc = qi_lb60_ooblayout_ecc,
110 struct nand_ecc_ctrl *ecc = &chip->ecc; in jz4725b_ooblayout_ecc() local
112 if (section || !ecc->total) in jz4725b_ooblayout_ecc()
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H A Djz4740_ecc.c3 * JZ4740 ECC controller driver
45 static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) in jz4740_ecc_reset() argument
50 writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_reset()
52 /* Initialize and enable ECC hardware */ in jz4740_ecc_reset()
53 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
57 if (calc_ecc) /* calculate ECC from data */ in jz4740_ecc_reset()
59 else /* correct data from ECC */ in jz4740_ecc_reset()
62 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
65 static int jz4740_ecc_calculate(struct ingenic_ecc *ecc, in jz4740_ecc_calculate() argument
73 jz4740_ecc_reset(ecc, true); in jz4740_ecc_calculate()
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/OK3568_Linux_fs/kernel/drivers/dma/ti/
H A Dedma.c228 struct edma_cc *ecc; member
309 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
311 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
314 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
316 __raw_writel(val, ecc->base + offset); in edma_write()
319 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
322 unsigned val = edma_read(ecc, offset); in edma_modify()
326 edma_write(ecc, offset, val); in edma_modify()
329 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) in edma_and() argument
331 unsigned val = edma_read(ecc, offset); in edma_and()
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/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Domap_gpmc.c94 * gen_true_ecc - This function will generate true ECC value, which
97 * @ecc_buf: buffer to store ecc code
99 * @return: re-formatted ECC value
108 * omap_correct_data - Compares the ecc read from nand spare area with ECC
116 * @read_ecc: ecc read from nand flash
117 * @calc_ecc: ecc read from ECC registers
128 /* Regenerate the orginal ECC */ in omap_correct_data()
131 /* Get the XOR of real ecc */ in omap_correct_data()
145 printf("Error: Ecc is wrong\n"); in omap_correct_data()
146 /* ECC itself is corrupted */ in omap_correct_data()
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H A Drockchip_nand.c211 struct nand_ecc_ctrl *ecc, in rockchip_nand_hw_ecc_setup() argument
218 ecc->strength = strength; in rockchip_nand_hw_ecc_setup()
219 ecc->bytes = DIV_ROUND_UP(ecc->strength * 14, 8); in rockchip_nand_hw_ecc_setup()
220 ecc->bytes = ALIGN(ecc->bytes, 2); in rockchip_nand_hw_ecc_setup()
222 switch (ecc->strength) { in rockchip_nand_hw_ecc_setup()
286 struct nand_ecc_ctrl *ecc = &chip->ecc; in rockchip_nand_read_extra_oob() local
287 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); in rockchip_nand_read_extra_oob()
301 struct nand_ecc_ctrl *ecc = &chip->ecc; in rockchip_nand_write_extra_oob() local
302 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); in rockchip_nand_write_extra_oob()
320 struct nand_ecc_ctrl *ecc = &chip->ecc; in rockchip_nand_hw_syndrome_pio_read_page() local
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H A Drockchip_nand_v9.c217 struct nand_ecc_ctrl *ecc, in rockchip_nand_hw_ecc_setup() argument
224 ecc->strength = strength; in rockchip_nand_hw_ecc_setup()
225 ecc->bytes = DIV_ROUND_UP(ecc->strength * 14, 8); in rockchip_nand_hw_ecc_setup()
226 ecc->bytes = ALIGN(ecc->bytes, 2); in rockchip_nand_hw_ecc_setup()
228 switch (ecc->strength) { in rockchip_nand_hw_ecc_setup()
287 struct nand_ecc_ctrl *ecc = &chip->ecc; in rockchip_nand_read_extra_oob() local
288 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); in rockchip_nand_read_extra_oob()
302 struct nand_ecc_ctrl *ecc = &chip->ecc; in rockchip_nand_write_extra_oob() local
303 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); in rockchip_nand_write_extra_oob()
321 struct nand_ecc_ctrl *ecc = &chip->ecc; in rockchip_nand_hw_syndrome_pio_read_page() local
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H A Dfsmc_nand.c25 * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
63 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
98 * ECC placement definitions in oobfree type format
99 * There are 13 bytes of ecc for every 512 byte block and it has to be read
102 * Managing the ecc bytes in the following way makes it easier for software to
103 * read ecc bytes consecutive to data bytes. This way is similar to
197 /* The calculated ecc is actually the correction index in data */ in fsmc_bch8_correct_data()
210 * would result in an ecc error because the oob data is also in fsmc_bch8_correct_data()
211 * erased to FF and the calculated ecc for an FF data is not in fsmc_bch8_correct_data()
262 const u_char *data, u_char *ecc) in fsmc_read_hwecc() argument
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H A Dzynq_nand.c37 (0x1 << 6)) /* Disable ECC interrupt */
55 #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
56 (0x1 << 4) | /* ECC read at end of page */ \
84 /* ECC block registers bit position and bit mask */
85 #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
86 #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
213 /* bbt decriptors for chips with on-die ECC and
239 * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
287 /* Wait till the ECC operation is complete */ in zynq_nand_init_nand_flash()
302 * zynq_nand_calculate_hwecc - Calculate Hardware ECC
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H A Dsunxi_nand.c213 * sunxi HW ECC infos: stores information related to HW ECC support
215 * @mode: the sunxi ECC mode field deduced from ECC requirements
216 * @layout: the OOB layout depending on the ECC requirements and the
217 * selected ECC mode
685 static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc) in sunxi_nfc_randomizer_state() argument
693 if (ecc) { in sunxi_nfc_randomizer_state()
704 int page, bool ecc) in sunxi_nfc_randomizer_config() argument
715 state = sunxi_nfc_randomizer_state(mtd, page, ecc); in sunxi_nfc_randomizer_config()
754 bool ecc, int page) in sunxi_nfc_randomizer_write_buf() argument
756 sunxi_nfc_randomizer_config(mtd, page, ecc); in sunxi_nfc_randomizer_write_buf()
[all …]
H A Dnand_base.c21 * if we have HW ECC support.
1677 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1681 * @ecc: ECC buffer
1682 * @ecclen: ECC length
1687 * Check if a data buffer and its associated ECC and OOB data contains only
1694 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1695 * different from the NAND page size. When fixing bitflips, ECC engines will
1702 * the payload data but also their associated ECC data, because a user might
1704 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1707 * data are protected by the ECC engine.
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/OK3568_Linux_fs/kernel/drivers/mtd/nand/
H A Decc.c3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
28 * - prepare: Prepare an I/O request. Enable/disable the ECC engine based on
30 * engine, this step may involve to derive the ECC bytes and place
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dnand-controller.yaml19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
49 nand-ecc-mode:
51 Desired ECC engine, either hardware (most of the time
54 and should be replaced by soft and nand-ecc-algo.
58 nand-ecc-engine:
62 A phandle on the hardware ECC engine if any. There are
64 1/ The ECC engine is part of the NAND controller, in this
66 2/ The ECC engine is part of the NAND part (on-die), in this
68 3/ The ECC engine is external, in this case the phandle should
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H A Dgpmc-nand.txt10 For NAND specific properties such as ECC modes or bus width, please refer to
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
31 "ham1" 1-bit Hamming ecc code
32 "bch4" 4-bit BCH ecc code
33 "bch8" 8-bit BCH ecc code
34 "bch16" 16-bit BCH ECC code
35 Refer below "How to select correct ECC scheme for your device ?"
47 locating ECC errors for BCHx algorithms. SoC devices which have
49 Using ELM for ECC error correction frees some CPU cycles.
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H A Dmtk-nand.txt5 the nand controller interface driver and the ECC engine driver.
23 - ecc-engine: Required ECC Engine node.
36 ecc-engine = <&bch>;
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
65 E : nand-ecc-strength.
71 Q : nand-ecc-step-size.
75 this number depends on max ecc step size
77 If max ecc step size supported is 1024,
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/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/boot-device/
H A Dboot-device-pro5.c16 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
28 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
29 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
[all …]
H A Dboot-device-ld4.c17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
25 {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
26 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
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H A Dboot-device-pxs2.c16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
25 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
[all …]
H A Dboot-device-ld11.c16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
25 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
[all …]

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