Searched +full:cros +full:- +full:ec +full:- +full:spi +full:- +full:pre +full:- +full:delay (Results 1 – 16 of 16) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Benson Leung <bleung@chromium.org>11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>12 - Guenter Roeck <groeck@chromium.org>15 Google's ChromeOS EC is a microcontroller which talks to the AP and17 The EC can be connected through various interfaces (I2C, SPI, and others)23 - description:[all …]
6 * SPDX-License-Identifier: GPL-2.09 #include <dt-bindings/clock/rockchip,rk808.h>10 #include <dt-bindings/input/input.h>11 #include "rk3288-veyron.dtsi"20 gpio_keys: gpio-keys {21 pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;26 linux,input-type = <5>; /* EV_SW */27 debounce-interval = <1>;28 gpio-key,wakeup;32 gpio-charger {[all …]
5 * SPDX-License-Identifier: GPL-2.0+10 u-boot,dm-pre-reloc;12 u-boot,dm-pre-reloc;16 spi@7000d400 {17 spi-deactivate-delay = <200>;18 spi-max-frequency = <3000000>;20 cros_ec: cros-ec@0 {21 ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
12 /dts-v1/;13 #include <dt-bindings/gpio/gpio.h>14 #include <dt-bindings/interrupt-controller/irq.h>15 #include <dt-bindings/input/input.h>32 spi0 = "/spi@12d20000";33 spi1 = "/spi@12d30000";34 spi2 = "/spi@12d40000";35 spi3 = "/spi@131a0000";36 spi4 = "/spi@131b0000";52 stdout-path = "serial3:115200n8";[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)9 #include <dt-bindings/clock/rockchip,rk808.h>10 #include <dt-bindings/input/input.h>11 #include "rk3288-veyron.dtsi"12 #include "rk3288-veyron-analog-audio.dtsi"13 #include "rk3288-veyron-edp.dtsi"14 #include "rk3288-veyron-sdmmc.dtsi"22 gpio-charger {23 compatible = "gpio-charger";24 charger-type = "mains";[all …]
1 // SPDX-License-Identifier: GPL-2.02 // SPI interface for ChromeOS Embedded Controller6 #include <linux/delay.h>14 #include <linux/spi/spi.h>23 * Number of EC preamble bytes we read at a time. Since it takes24 * about 400-500us for the EC to respond there is not a lot of25 * point in tuning this. If the EC could respond faster then28 * SPI transfer size is 256 bytes, so at 5MHz we need a response34 * Allow for a long time for the EC to respond. We support i2c50 * for this, clocking in at 2-3ms.[all …]
1 /dts-v1/;3 #include <dt-bindings/gpio/x86-gpio.h>14 compatible = "google,link", "intel,celeron-ivybridge";17 spi0 = &spi;27 #address-cells = <1>;28 #size-cells = <0>;29 u-boot,dm-pre-reloc;33 compatible = "intel,core-gen3";35 intel,apic-id = <0>;36 u-boot,dm-pre-reloc;[all …]
1 /dts-v1/;3 #include <dt-bindings/gpio/x86-gpio.h>17 spi0 = &spi;27 #address-cells = <1>;28 #size-cells = <0>;32 compatible = "intel,core-i3-gen5";34 intel,apic-id = <0>;35 intel,slow-ramp = <3>;40 compatible = "intel,core-i3-gen5";42 intel,apic-id = <1>;[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */3 * Host communication command constants for ChromeOS EC7 * NOTE: This file is auto-generated from ChromeOS EC Open Source code from8 * https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/ec_commands.h11 /* Host communication command constants for Chrome EC */52 * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff59 /* EC command register bit functions */61 #define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */62 #define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */73 #define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */[all …]
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
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... pax_global_header qtwebengine-chromium-0ad2814370799a2161057d92231fe3ee00e2fe98/ qtwebengine-chromium-0ad2814370799a2161057d92231fe3ee00e2fe98/chromium/ qtwebengine-chromium- ...