| /OK3568_Linux_fs/kernel/include/linux/ |
| H A D | lcd.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2003,2004 Hewlett-Packard Company
19 * lcd_device->ops_lock is an internal backlight lock protecting the ops
36 /* The maximum value for contrast (read-only) */
41 /* Get the LCD panel power status (0: full on, 1..3: controller
42 power on, flat panel power off, 4: full off), see FB_BLANK_XXX */
44 /* Enable or disable power to the LCD (0: on; 4: off, see FB_BLANK_XXX) */
45 int (*set_power)(struct lcd_device *, int power);
46 /* Get the current contrast setting (0-max_contrast) */
77 lcd power off and 1, lcd power on. */
[all …]
|
| H A D | clocksource.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <linux/time.h>
34 * struct clocksource - hardware abstraction for a free running counter
35 * Provides mostly state-free accessors to the underlying hardware.
36 * This is the structure used for system time.
42 * @shift: Cycle to nanosecond divisor (power of two)
43 * @max_idle_ns: Maximum idle time permitted by the clocksource (nsecs)
45 * @archdata: Optional arch-specific data
54 * 1-99: Unfit for real use
56 * 100-199: Base level usability.
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/tegra/ |
| H A D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | cpu.c | 5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/pmc.h>
17 #include <asm/arch-tegra/ap.h>
20 /* Tegra124-specific CPU init code */
28 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ in enable_cpu_power_rail()
35 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), in enable_cpu_power_rail()
38 writel(0x7C830, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
41 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); in enable_cpu_power_rail()
42 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); in enable_cpu_power_rail()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_pm_internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved.
18 * http://www.gnu.org/licenses/gpl-2.0.html.
23 * Power management API definitions used internally by GPU backend
36 * kbase_pm_dev_idle - The GPU is idle.
45 * kbase_pm_dev_activate - The GPU is active.
54 * kbase_pm_get_present_cores - Get details of the cores that are present in
61 * This function can be called by the active power policy to return a bitmask of
71 * kbase_pm_get_active_cores - Get details of the cores that are currently
77 * This function can be called by the active power policy to return a bitmask of
[all …]
|
| /OK3568_Linux_fs/kernel/arch/parisc/kernel/ |
| H A D | firmware.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/parisc/kernel/firmware.c - safe PDC access routines
14 * Copyright 2003 Grant Grundler <grundler parisc-linux org>
15 * Copyright 2003,2004 Ryan Bradetich <rbrad@parisc-linux.org>
16 * Copyright 2004,2006 Thibaut VARENE <varenet@parisc-linux.org>
22 * - the name of the pdc wrapper should match one of the macros
24 * - don't use caps for random parts of the name
25 * - use the static PDC result buffers and "copyout" to structs
27 * - hold pdc_lock while in PDC or using static result buffers
28 * - use __pa() to convert virtual (kernel) pointers to physical
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/w1/slaves/ |
| H A D | w1_ds28e17.rst | 7 * Maxim DS28E17 1-Wire-to-I2C Master Bridge
19 -----------
30 SUBSYSTEM=="i2c-dev", KERNEL=="i2c-[0-9]*", ATTRS{name}=="w1-19-*", \
31 SYMLINK+="i2c-$attr{name}"
33 may be used to create stable /dev/i2c- entries based on the unique id of the
41 it is connected. The power-on default of the DS28E17 is 400kBaud, but
42 chips may come and go on the Onewire bus without being de-powered and
44 reconnected DS28E17 device on the Onewire bus, it will re-apply this
53 wait time for an I2C transfer. This is to account for I2C slave devices
55 needed timeout cannot be pre-calculated correctly. As the w1_ds28e17
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/media/i2c/ |
| H A D | vs6624_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * vs6624 - ST VS6624 CMOS image sensor registers
12 #define VS6624_MICRO_EN 0xC003 /* power enable for all MCU clock */
101 /* power management */
102 #define VS6624_TIME_TO_POWER_DOWN 0x0580 /* automatically transition time to stop mode */
110 #define VS6624_LIGHT_FREQ 0x0C80 /* AC frequency used for flicker free time */
123 #define VS6624_EXPO_TIME_NUM 0x1184 /* exposure time numerator */
124 #define VS6624_EXPO_TIME_DEN 0x1186 /* exposure time denominator */
125 #define VS6624_EXPO_TIME_MSB 0x1189 /* exposure time for the Manual Mode MSB */
126 #define VS6624_EXPO_TIME_LSB 0x118A /* exposure time for the Manual Mode LSB */
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/driver-api/usb/ |
| H A D | usb.rst | 1 .. _usb-hostside-api:
4 The Linux-USB Host Side API
18 That master/slave asymmetry was designed-in for a number of reasons, one
22 distributed auto-configuration since the pre-designated master node
29 measurement and improved power management introduced.
37 USB Host-Side API Model
40 Host-side drivers for USB devices talk to the "usbcore" APIs. There are
41 two. One is intended for *general-purpose* drivers (exposed through
49 - USB supports four kinds of data transfers (control, bulk, interrupt,
54 - The device description model includes one or more "configurations"
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | cpu.c | 2 * (C) Copyright 2010-2014
5 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/pmc.h>
18 /* Tegra114-specific CPU init code */
27 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ in enable_cpu_power_rail()
32 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), in enable_cpu_power_rail()
36 writel(reg, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
39 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); in enable_cpu_power_rail()
40 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); in enable_cpu_power_rail()
[all …]
|
| /OK3568_Linux_fs/yocto/poky/bitbake/doc/bitbake-user-manual/ |
| H A D | bitbake-user-manual-intro.rst | 1 .. SPDX-License-Identifier: CC-BY-2.5
23 working within complex inter-task dependency constraints. One of
25 Linux software stacks using a task-oriented approach.
30 - BitBake executes tasks according to the provided metadata that builds up
37 - BitBake includes a fetcher library for obtaining source code from
41 - The instructions for each unit to be built (e.g. a piece of software)
46 - BitBake includes a client/server abstraction and can be used from a
47 command line or used as a service over XML-RPC and has several
58 - BitBake, a generic task executor
60 - OpenEmbedded, a metadata set utilized by BitBake
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/virt/kvm/ |
| H A D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
23 time introduces a new set of challenges because it introduces a multiplexed
24 division of time beyond the control of the guest CPU.
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/pl111/ |
| H A D | pl111_display.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
7 * Copyright (c) 2006-2008 Intel Corporation
15 #include <linux/dma-buf.h>
32 irq_stat = readl(priv->regs + CLCD_PL111_MIS); in pl111_irq()
38 drm_crtc_handle_vblank(&priv->pipe.crtc); in pl111_irq()
44 writel(irq_stat, priv->regs + CLCD_PL111_ICR); in pl111_irq()
53 struct drm_device *drm = pipe->crtc.dev; in pl111_mode_valid()
54 struct pl111_drm_dev_private *priv = drm->dev_private; in pl111_mode_valid()
55 u32 cpp = priv->variant->fb_bpp / 8; in pl111_mode_valid()
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/process/ |
| H A D | 6.Followthrough.rst | 23 ----------------------
31 - If you have explained your patch well, reviewers will understand its
35 Many of the changes you may be asked to make - from coding style tweaks
36 to substantial rewrites - come from the understanding that Linux will
39 - Code review is hard work, and it is a relatively thankless occupation;
47 - Similarly, code reviewers are not trying to promote their employers'
57 from happening. When you get review comments on a patch, take the time to
68 agree with the reviewer, take some time to think things over again. It can
75 can help future reviewers avoid the questions which came up the first time
80 responded to the comments you got the time before, you're likely to find
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/fw/api/ |
| H A D | soc.h | 8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
9 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
10 * Copyright(c) 2012 - 2014, 2019 - 2020 Intel Corporation
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
31 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
32 * Copyright(c) 2012 - 2014, 2019 - 2020 Intel Corporation
76 * struct iwl_soc_configuration_cmd - Set device stabilization latency
81 * @latency: time for SOC to ensure stable power & XTAL
|
| /OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/mxs/ |
| H A D | spl_power_init.c | 7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
25 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
40 &clkctrl_regs->hw_clkctrl_clkseq_set); in mxs_power_clock2xtal()
44 * mxs_power_clock2pll() - Switch CPU core clock source to PLL
47 * to PLL. This can only be called once the PLL has re-locked and once
48 * the PLL is stable after reconfiguration.
62 * we aren't giving PLL0 enough time to stabilise? in mxs_power_clock2pll()
64 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, in mxs_power_clock2pll()
72 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, in mxs_power_clock2pll()
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/driver-api/ |
| H A D | rfkill.rst | 2 rfkill - RF kill switch support
14 radiate any power.
25 - hard block
26 read-only radio block that cannot be overridden by software
28 - soft block
34 admin-guide/kernel-parameters.rst.
43 * the deprecated rfkill-input module (an input layer handler, being
49 the system know about hardware-disabled states that may be implemented on
56 When the device is hard-blocked (either by a call to rfkill_set_hw_state()
77 core with the current state at resume time.
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | mipi_dsim.h | 7 * SPDX-License-Identifier: GPL-2.0+
63 /* MIPI DSI Processor-to-Peripheral transaction types */
112 * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
140 * in Non-burst mode, RGB data area is filled with RGB data and NULL
148 * if the timer value goes to 0x00000000, the clock stable bit of status
155 * BTA requests to D-PHY automatically. this counter value specifies
158 * this register specifies time out from BTA request to change
161 * this register specifies time out on how long RxValid deasserts,
163 * - RxValid specifies Rx data valid indicator.
164 * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/ |
| H A D | mmc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
46 non-removable:
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/memory/samsung/ |
| H A D | exynos5422-dmc.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/devfreq-event.h>
100 * struct dmc_opp_table - Operating level desciption
112 * struct exynos5_dmc - main structure describing DMC device
127 * @timing_power: balues for timing power register, for each OPP
132 * @bypass_timing_power: value for timing power register for bypass
143 * @last_overflow_ts: time (in ns) of last overflow of each DREX
145 * @total: total time between devfreq events
195 __val = (t_val) << (timing)->bit_beg; \
219 TIMING_FIELD("tW2W-C2C", 14, 14),
[all …]
|
| /OK3568_Linux_fs/kernel/sound/soc/codecs/ |
| H A D | rk3308_codec.c | 2 * rk3308_codec.c -- RK3308 ALSA Soc Audio Driver
54 #define CODEC_DRV_NAME "rk3308-acodec"
137 PM_LLP_DOWN, /* light low power down */
139 PM_DLP_DOWN, /* deep low power down */
167 * grp 0 -- select ADC1 / ADC2
168 * grp 1 -- select ADC3 / ADC4
169 * grp 2 -- select ADC5 / ADC6
170 * grp 3 -- select ADC7 / ADC8
204 /* Only hpout do fade-in and fade-out */
228 -1800, 150, 2850);
[all …]
|
| /OK3568_Linux_fs/kernel/include/linux/input/ |
| H A D | adxl34x.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
58 * is an unsigned time value representing the maximum
59 * time that an event must be above the tap_threshold threshold
68 * is an unsigned time value representing the wait time
69 * from the detection of a tap event to the opening of the time
79 * is an unsigned time value representing the amount
80 * of time after the expiration of tap_latency during which a second
145 * is an unsigned time value representing the
146 * amount of time that acceleration must be below the value in
152 * result in the function appearing un-responsive if the
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/mmc/host/ |
| H A D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
65 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/rtc/ |
| H A D | rtc-sirfsoc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SiRFSoC Real Time Clock interface for Linux
38 /* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
48 /* Overflow for every 8 years extra time */
62 regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val); in sirfsoc_rtc_readl()
69 regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val); in sirfsoc_rtc_writel()
80 spin_lock_irq(&rtcdrv->lock); in sirfsoc_rtc_read_alarm()
89 * 0->0xffffffff in sirfsoc_rtc_read_alarm()
93 rtc_time64_to_tm((rtcdrv->overflow_rtc + 1) in sirfsoc_rtc_read_alarm()
94 << (BITS_PER_LONG - RTC_SHIFT) in sirfsoc_rtc_read_alarm()
[all …]
|
| /OK3568_Linux_fs/u-boot/drivers/mmc/ |
| H A D | xenon_sdhci.c | 7 * Date: 2016-8-24
12 * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
15 * SPDX-License-Identifier: GPL-2.0
27 /* Register Offset of SD Host Controller SOCP self-defined register */
122 struct xenon_sdhci_priv *priv = host->mmc->priv; in xenon_mmc_phy_init()
123 u32 clock = priv->clock; in xenon_mmc_phy_init()
124 u32 time; in xenon_mmc_phy_init() local
130 if ((priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_init()
131 (priv->timing == MMC_TIMING_UHS_SDR25) || in xenon_mmc_phy_init()
132 (priv->timing == MMC_TIMING_UHS_SDR12) || in xenon_mmc_phy_init()
[all …]
|