Lines Matching +full:power +full:- +full:stable +full:- +full:time
7 * Date: 2016-8-24
12 * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
15 * SPDX-License-Identifier: GPL-2.0
27 /* Register Offset of SD Host Controller SOCP self-defined register */
122 struct xenon_sdhci_priv *priv = host->mmc->priv; in xenon_mmc_phy_init()
123 u32 clock = priv->clock; in xenon_mmc_phy_init()
124 u32 time; in xenon_mmc_phy_init() local
130 if ((priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_init()
131 (priv->timing == MMC_TIMING_UHS_SDR25) || in xenon_mmc_phy_init()
132 (priv->timing == MMC_TIMING_UHS_SDR12) || in xenon_mmc_phy_init()
133 (priv->timing == MMC_TIMING_SD_HS) || in xenon_mmc_phy_init()
134 (priv->timing == MMC_TIMING_LEGACY)) in xenon_mmc_phy_init()
138 /* Poll for host MMC PHY clock init to be stable */ in xenon_mmc_phy_init()
140 time = 100; in xenon_mmc_phy_init()
141 while (time--) { in xenon_mmc_phy_init()
149 if (time <= 0) { in xenon_mmc_phy_init()
150 pr_err("Failed to enable MMC internal clock in time\n"); in xenon_mmc_phy_init()
151 return -ETIMEDOUT; in xenon_mmc_phy_init()
166 time = 100; in xenon_mmc_phy_init()
167 while (time--) { in xenon_mmc_phy_init()
177 if (time <= 0) { in xenon_mmc_phy_init()
178 pr_err("Failed to init MMC PHY in time\n"); in xenon_mmc_phy_init()
179 return -ETIMEDOUT; in xenon_mmc_phy_init()
190 struct xenon_sdhci_priv *priv = host->mmc->priv; in armada_3700_soc_pad_voltage_set()
192 if (priv->pad_type == SOC_PAD_FIXED_1_8V) in armada_3700_soc_pad_voltage_set()
193 writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg); in armada_3700_soc_pad_voltage_set()
194 else if (priv->pad_type == SOC_PAD_SD) in armada_3700_soc_pad_voltage_set()
195 writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg); in armada_3700_soc_pad_voltage_set()
200 struct xenon_sdhci_priv *priv = host->mmc->priv; in xenon_mmc_phy_set()
219 if ((priv->timing == MMC_TIMING_MMC_HS400) || in xenon_mmc_phy_set()
220 (priv->timing == MMC_TIMING_MMC_HS200) || in xenon_mmc_phy_set()
221 (priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_set()
222 (priv->timing == MMC_TIMING_UHS_SDR104) || in xenon_mmc_phy_set()
223 (priv->timing == MMC_TIMING_UHS_DDR50) || in xenon_mmc_phy_set()
224 (priv->timing == MMC_TIMING_UHS_SDR25) || in xenon_mmc_phy_set()
225 (priv->timing == MMC_TIMING_MMC_DDR52)) { in xenon_mmc_phy_set()
240 if (mmc_card_ddr(host->mmc)) { in xenon_mmc_phy_set()
296 /* Clear the Re-Tuning Request functionality */ in xenon_mmc_disable_tuning()
301 /* Clear the Re-tuning Event Signal Enable */ in xenon_mmc_disable_tuning()
320 struct xenon_sdhci_priv *priv = host->mmc->priv; in xenon_sdhci_set_ios_post()
321 uint speed = host->mmc->clock; in xenon_sdhci_set_ios_post()
329 if (IS_SD(host->mmc)) { in xenon_sdhci_set_ios_post()
332 if (mmc_card_ddr(host->mmc)) in xenon_sdhci_set_ios_post()
333 priv->timing = MMC_TIMING_UHS_DDR50; in xenon_sdhci_set_ios_post()
335 priv->timing = MMC_TIMING_UHS_SDR25; in xenon_sdhci_set_ios_post()
337 priv->timing = MMC_TIMING_UHS_SDR50; in xenon_sdhci_set_ios_post()
340 priv->timing = MMC_TIMING_LEGACY; in xenon_sdhci_set_ios_post()
342 priv->timing = MMC_TIMING_SD_HS; in xenon_sdhci_set_ios_post()
346 if (mmc_card_ddr(host->mmc)) in xenon_sdhci_set_ios_post()
347 priv->timing = MMC_TIMING_MMC_DDR52; in xenon_sdhci_set_ios_post()
349 priv->timing = MMC_TIMING_LEGACY; in xenon_sdhci_set_ios_post()
351 priv->timing = MMC_TIMING_MMC_HS; in xenon_sdhci_set_ios_post()
354 /* Re-init the PHY */ in xenon_sdhci_set_ios_post()
371 host->mmc = &plat->mmc; in xenon_sdhci_probe()
372 host->mmc->priv = host; in xenon_sdhci_probe()
373 host->mmc->dev = dev; in xenon_sdhci_probe()
374 upriv->mmc = host->mmc; in xenon_sdhci_probe()
377 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR; in xenon_sdhci_probe()
380 priv->timing = MMC_TIMING_LEGACY; in xenon_sdhci_probe()
389 * Set default power on SoC PHY PAD register (currently only in xenon_sdhci_probe()
392 if (priv->pad_ctrl_reg) in xenon_sdhci_probe()
395 host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz; in xenon_sdhci_probe()
396 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", in xenon_sdhci_probe()
399 host->host_caps |= MMC_MODE_8BIT; in xenon_sdhci_probe()
402 host->host_caps |= MMC_MODE_4BIT; in xenon_sdhci_probe()
407 printf("Invalid \"bus-width\" value\n"); in xenon_sdhci_probe()
408 return -EINVAL; in xenon_sdhci_probe()
411 host->ops = &xenon_sdhci_ops; in xenon_sdhci_probe()
413 host->max_clk = XENON_MMC_MAX_CLK; in xenon_sdhci_probe()
414 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); in xenon_sdhci_probe()
442 host->name = dev->name; in xenon_sdhci_ofdata_to_platdata()
443 host->ioaddr = (void *)devfdt_get_addr(dev); in xenon_sdhci_ofdata_to_platdata()
445 if (device_is_compatible(dev, "marvell,armada-3700-sdhci")) in xenon_sdhci_ofdata_to_platdata()
446 priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1); in xenon_sdhci_ofdata_to_platdata()
448 name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type", in xenon_sdhci_ofdata_to_platdata()
452 priv->pad_type = SOC_PAD_SD; in xenon_sdhci_ofdata_to_platdata()
453 } else if (0 == strncmp(name, "fixed-1-8v", 10)) { in xenon_sdhci_ofdata_to_platdata()
454 priv->pad_type = SOC_PAD_FIXED_1_8V; in xenon_sdhci_ofdata_to_platdata()
457 return -EINVAL; in xenon_sdhci_ofdata_to_platdata()
468 return sdhci_bind(dev, &plat->mmc, &plat->cfg); in xenon_sdhci_bind()
472 { .compatible = "marvell,armada-8k-sdhci",},
473 { .compatible = "marvell,armada-3700-sdhci",},