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18 Secondary GICs are cascaded into the upward interrupt controller and do not105 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
145 * chips and call this to register their GICs.
47 * "performance interrupt". Luckily, on compliant GICs the polarity is in arm_pmu_acpi_register_irq()
629 MADT for GICs are expected to be in synchronization. The _UID of the Device698 - Section 9.17: I/O APIC devices; all GICs must be enumerable via MADT
522 * because any nested/secondary GICs do not directly interface in gic_cpu_init()1271 * For primary GICs, skip over SGIs. in gic_init_bases()