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/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c924 tRPST = (last->emc_mrw & 0x80) >> 7; in tegra210_emc_r21021_set_clock()
994 emc_writel(emc, next->emc_mrw, EMC_MRW); in tegra210_emc_r21021_set_clock()
1078 emc_writel(emc, value, EMC_MRW); in tegra210_emc_r21021_set_clock()
1509 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1543 EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1550 ccfifo_writel(emc, value, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
H A Dtegra210-emc.h87 #define EMC_MRW 0xe8 macro
850 u32 emc_mrw; member
H A Dtegra30-emc.c78 #define EMC_MRW 0x0e8 macro
718 emc->regs + EMC_MRW); in emc_prepare_timing_change()
722 emc->regs + EMC_MRW); in emc_prepare_timing_change()
H A Dtegra124-emc.c103 #define EMC_MRW 0xe8 macro
765 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
/OK3568_Linux_fs/kernel/arch/arm/mach-tegra/
H A Dsleep-tegra30.S23 #define EMC_MRW 0xe8 macro
505 str r2, [r0, #EMC_MRW]
515 str r2, [r0, #EMC_MRW]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra20/
H A Demc.h68 u32 mrw; /* 0xE8: EMC_MRW */
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml105 value of the EMC_MRW register for this set of timings