Searched +full:0 +full:xfd7c0000 (Results 1 – 5 of 5) sorted by relevance
60 reg = <0xfd7c0000 0x5c000>;
22 printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \24 } while (0)27 #define PCIE_SNPS_DBI_BASE 0xf500000028 #define PCIE_SNPS_APB_BASE 0xfe15000029 #define PCIE_SNPS_IATU_BASE 0xa4030000031 #define PCI_RESBAR 0x2e833 #define PCIE_SNPS_DBI_BASE 0xf600000034 #define PCIE_SNPS_APB_BASE 0xfe28000035 #define PCIE_SNPS_IATU_BASE 0x3c0b0000037 #define PCI_RESBAR 0x2b8[all …]
19 #define FIREWALL_DDR_BASE 0xfe03000020 #define FW_DDR_MST5_REG 0x5421 #define FW_DDR_MST13_REG 0x7422 #define FW_DDR_MST19_REG 0x8c23 #define FW_DDR_MST21_REG 0x9424 #define FW_DDR_MST26_REG 0xa825 #define FW_DDR_MST27_REG 0xac26 #define FIREWALL_SYSMEM_BASE 0xfe03800027 #define FW_SYSM_MST5_REG 0x5428 #define FW_SYSM_MST13_REG 0x74[all …]
56 #size-cells = <0>;91 cpu_l0: cpu@0 {94 reg = <0x0>;102 reg = <0x100>;110 reg = <0x200>;118 reg = <0x300>;126 reg = <0x400>;134 reg = <0x500>;142 reg = <0x600>;150 reg = <0x700>;[all …]
89 #clock-cells = <0>;96 #clock-cells = <0>;103 #clock-cells = <0>;110 reg = <0 0xfd7c08ec 0 0x10>;114 #clock-cells = <0>;119 reg = <0 0xfd7c08b0 0 0x10>;123 #clock-cells = <0>;128 reg = <0 0xfd7c08dc 0 0x10>;132 #clock-cells = <0>;137 reg = <0 0xfd7c08a8 0 0x10>;[all …]