1 /*
2 * Copyright (c) 2021 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <dm.h>
8 #include <misc.h>
9 #include <mmc.h>
10 #include <spl.h>
11 #include <asm/io.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/ioc_rk3588.h>
15 #include <dt-bindings/clock/rk3588-cru.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define FIREWALL_DDR_BASE 0xfe030000
20 #define FW_DDR_MST5_REG 0x54
21 #define FW_DDR_MST13_REG 0x74
22 #define FW_DDR_MST19_REG 0x8c
23 #define FW_DDR_MST21_REG 0x94
24 #define FW_DDR_MST26_REG 0xa8
25 #define FW_DDR_MST27_REG 0xac
26 #define FIREWALL_SYSMEM_BASE 0xfe038000
27 #define FW_SYSM_MST5_REG 0x54
28 #define FW_SYSM_MST13_REG 0x74
29 #define FW_SYSM_MST19_REG 0x8c
30 #define FW_SYSM_MST21_REG 0x94
31 #define FW_SYSM_MST26_REG 0xa8
32 #define FW_SYSM_MST27_REG 0xac
33 #define PMU1_SGRF_BASE 0xfd582000
34 #define PMU1_SGRF_SOC_CON0 0x0
35 #define PMU1_SGRF_SOC_CON6 0x18
36 #define PMU1_SGRF_SOC_CON7 0x1c
37 #define PMU1_SGRF_SOC_CON8 0x20
38 #define PMU1_SGRF_SOC_CON9 0x24
39 #define PMU1_SGRF_SOC_CON10 0x28
40 #define PMU1_SGRF_SOC_CON13 0x34
41 #define SYS_GRF_BASE 0xfd58c000
42 #define SYS_GRF_SOC_CON6 0x0318
43 #define USBGRF_BASE 0xfd5ac000
44 #define USB_GRF_USB3OTG0_CON1 0x001c
45 #define BUS_SGRF_BASE 0xfd586000
46 #define BUS_SGRF_SOC_CON2 0x08
47 #define BUS_SGRF_FIREWALL_CON18 0x288
48 #define PMU_BASE 0xfd8d0000
49 #define PMU_PWR_GATE_SFTCON1 0x8150
50
51 #define USB2PHY1_GRF_BASE 0xfd5d4000
52 #define USB2PHY2_GRF_BASE 0xfd5d8000
53 #define USB2PHY3_GRF_BASE 0xfd5dc000
54 #define USB2PHY_GRF_CON2 0x0008
55
56 #define PMU1_IOC_BASE 0xfd5f0000
57 #define PMU2_IOC_BASE 0xfd5f4000
58
59 #define BUS_IOC_BASE 0xfd5f8000
60 #define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
61 #define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
62 #define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
63 #define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
64 #define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
65
66 #define VCCIO3_5_IOC_BASE 0xfd5fa000
67 #define IOC_VCCIO3_5_GPIO2A_DS_H 0x44
68 #define IOC_VCCIO3_5_GPIO2B_DS_L 0x48
69 #define IOC_VCCIO3_5_GPIO2B_DS_H 0x4c
70 #define IOC_VCCIO3_5_GPIO3A_DS_L 0x60
71 #define IOC_VCCIO3_5_GPIO3A_DS_H 0x64
72 #define IOC_VCCIO3_5_GPIO3C_DS_H 0x74
73
74 #define EMMC_IOC_BASE 0xfd5fd000
75 #define EMMC_IOC_GPIO2A_DS_L 0x40
76 #define EMMC_IOC_GPIO2D_DS_L 0x58
77 #define EMMC_IOC_GPIO2D_DS_H 0x5c
78
79 #define CRU_BASE 0xfd7c0000
80 #define CRU_GPLL_CON1 0x01c4
81 #define CRU_SOFTRST_CON77 0x0b34
82 #define CRU_GLB_RST_CON 0x0c10
83
84 #define PMU1CRU_BASE 0xfd7f0000
85 #define PMU1CRU_SOFTRST_CON00 0x0a00
86 #define PMU1CRU_SOFTRST_CON03 0x0a0c
87 #define PMU1CRU_SOFTRST_CON04 0x0a10
88
89 #define HDMIRX_NODE_FDT_PATH "/hdmirx-controller@fdee0000"
90 #define RK3588_PHY_CONFIG 0xfdee00c0
91
92 #define VOP_M0_PRIORITY_REG 0xfdf82008
93 #define VOP_M1_PRIORITY_REG 0xfdf82208
94 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
95
96 #ifdef CONFIG_ARM64
97 #include <asm/armv8/mmu.h>
98
99 static struct mm_region rk3588_mem_map[] = {
100 {
101 .virt = 0x0UL,
102 .phys = 0x0UL,
103 .size = 0xf0000000UL,
104 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
105 PTE_BLOCK_INNER_SHARE
106 }, {
107 .virt = 0xf0000000UL,
108 .phys = 0xf0000000UL,
109 .size = 0x10000000UL,
110 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
111 PTE_BLOCK_NON_SHARE |
112 PTE_BLOCK_PXN | PTE_BLOCK_UXN
113 }, {
114 .virt = 0x900000000,
115 .phys = 0x900000000,
116 .size = 0x150000000,
117 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
118 PTE_BLOCK_NON_SHARE |
119 PTE_BLOCK_PXN | PTE_BLOCK_UXN
120 }, {
121 /* List terminator */
122 0,
123 }
124 };
125
126 struct mm_region *mem_map = rk3588_mem_map;
127 #endif
128
129 /* GPIO0B_IOMUX_SEL_L */
130 enum {
131 GPIO0B0_SHIFT = 0,
132 GPIO0B0_MASK = GENMASK(3, 0),
133 GPIO0B0_UART0_RX_M1 = 4,
134
135 GPIO0B1_SHIFT = 4,
136 GPIO0B1_MASK = GENMASK(7, 4),
137 GPIO0B1_UART0_TX_M1 = 4,
138 };
139
140 /* GPIO0C_IOMUX_SEL_H */
141 enum {
142 GPIO0C4_SHIFT = 0,
143 GPIO0C4_MASK = GENMASK(3, 0),
144 GPIO0C4_UART0_RX_M0 = 4,
145
146 GPIO0C5_SHIFT = 4,
147 GPIO0C5_MASK = GENMASK(7, 4),
148 GPIO0C5_UART0_TX_M0 = 4,
149 };
150
151 /* GPIO0B_IOMUX_SEL_H */
152 enum {
153 GPIO0B5_SHIFT = 4,
154 GPIO0B5_MASK = GENMASK(7, 4),
155 GPIO0B5_REFER = 8,
156 GPIO0B5_UART2_TX_M0 = 10,
157
158 GPIO0B6_SHIFT = 8,
159 GPIO0B6_MASK = GENMASK(11, 8),
160 GPIO0B6_REFER = 8,
161 GPIO0B6_UART2_RX_M0 = 10,
162 };
163
164 /* GPIO0D_IOMUX_SEL_L */
165 enum {
166 GPIO0D1_SHIFT = 4,
167 GPIO0D1_MASK = GENMASK(7, 4),
168 GPIO0D1_REFER = 8,
169 GPIO0D1_UART1_TX_M2 = 10,
170
171 GPIO0D2_SHIFT = 8,
172 GPIO0D2_MASK = GENMASK(11, 8),
173 GPIO0D2_REFER = 8,
174 GPIO0D2_UART1_RX_M2 = 10,
175 };
176
177 /* GPIO1A_IOMUX_SEL_L */
178 enum {
179 GPIO1A0_SHIFT = 0,
180 GPIO1A0_MASK = GENMASK(3, 0),
181 GPIO1A0_UART6_RX_M1 = 10,
182
183 GPIO1A1_SHIFT = 4,
184 GPIO1A1_MASK = GENMASK(7, 4),
185 GPIO1A1_UART6_TX_M1 = 10,
186 };
187
188 /* GPIO1B_IOMUX_SEL_L */
189 enum {
190 GPIO1B2_SHIFT = 8,
191 GPIO1B2_MASK = GENMASK(11, 8),
192 GPIO1B2_UART4_RX_M2 = 10,
193
194 GPIO1B3_SHIFT = 12,
195 GPIO1B3_MASK = GENMASK(15, 12),
196 GPIO1B3_UART4_TX_M2 = 10,
197 };
198
199 /* GPIO1B_IOMUX_SEL_H */
200 enum {
201 GPIO1B4_SHIFT = 0,
202 GPIO1B4_MASK = GENMASK(3, 0),
203 GPIO1B4_UART7_RX_M2 = 10,
204
205 GPIO1B5_SHIFT = 4,
206 GPIO1B5_MASK = GENMASK(7, 4),
207 GPIO1B5_UART7_TX_M2 = 10,
208
209 GPIO1B6_SHIFT = 8,
210 GPIO1B6_MASK = GENMASK(11, 8),
211 GPIO1B6_UART1_TX_M1 = 10,
212
213 GPIO1B7_SHIFT = 12,
214 GPIO1B7_MASK = GENMASK(15, 12),
215 GPIO1B7_UART1_RX_M1 = 10,
216 };
217
218 /* GPIO1C_IOMUX_SEL_L */
219 enum {
220 GPIO1C0_SHIFT = 0,
221 GPIO1C0_MASK = GENMASK(3, 0),
222 GPIO1C0_UART3_RX_M0 = 10,
223
224 GPIO1C1_SHIFT = 4,
225 GPIO1C1_MASK = GENMASK(7, 4),
226 GPIO1C1_UART3_TX_M0 = 10,
227 };
228
229 /* GPIO1D_IOMUX_SEL_L */
230 enum {
231 GPIO1D0_SHIFT = 0,
232 GPIO1D0_MASK = GENMASK(3, 0),
233 GPIO1D0_UART6_TX_M2 = 10,
234
235 GPIO1D1_SHIFT = 4,
236 GPIO1D1_MASK = GENMASK(7, 4),
237 GPIO1D1_UART6_RX_M2 = 10,
238
239 GPIO1D2_SHIFT = 8,
240 GPIO1D2_MASK = GENMASK(11, 8),
241 GPIO1D2_UART4_TX_M0 = 10,
242
243 GPIO1D3_SHIFT = 12,
244 GPIO1D3_MASK = GENMASK(15, 12),
245 GPIO1D3_UART4_RX_M0 = 10,
246 };
247
248 /* GPIO2A_IOMUX_SEL_H */
249 enum {
250 GPIO2A6_SHIFT = 8,
251 GPIO2A6_MASK = GENMASK(11, 8),
252 GPIO2A6_UART6_RX_M0 = 10,
253
254 GPIO2A7_SHIFT = 12,
255 GPIO2A7_MASK = GENMASK(15, 12),
256 GPIO2A7_UART6_TX_M0 = 10,
257 };
258
259 /* GPIO2B_IOMUX_SEL_H */
260 enum {
261 GPIO2B4_SHIFT = 0,
262 GPIO2B4_MASK = GENMASK(3, 0),
263 GPIO2B4_UART7_RX_M0 = 10,
264
265 GPIO2B5_SHIFT = 4,
266 GPIO2B5_MASK = GENMASK(7, 4),
267 GPIO2B5_UART7_TX_M0 = 10,
268
269 GPIO2B6_SHIFT = 8,
270 GPIO2B6_MASK = GENMASK(11, 8),
271 GPIO2B6_UART1_RX_M0 = 10,
272
273 GPIO2B7_SHIFT = 12,
274 GPIO2B7_MASK = GENMASK(15, 12),
275 GPIO2B7_UART1_TX_M0 = 10,
276 };
277
278 /* GPIO2C_IOMUX_SEL_L */
279 enum {
280 GPIO2C2_SHIFT = 8,
281 GPIO2C2_MASK = GENMASK(11, 8),
282 GPIO2C2_UART9_TX_M0 = 10,
283 };
284
285 /* GPIO2C_IOMUX_SEL_H */
286 enum {
287 GPIO2C4_SHIFT = 0,
288 GPIO2C4_MASK = GENMASK(3, 0),
289 GPIO2C4_UART9_RX_M0 = 10,
290 };
291
292 /* GPIO2D_IOMUX_SEL_H */
293 enum {
294 GPIO2D4_SHIFT = 0,
295 GPIO2D4_MASK = GENMASK(3, 0),
296 GPIO2D4_UART5_RX_M2 = 10,
297
298 GPIO2D5_SHIFT = 4,
299 GPIO2D5_MASK = GENMASK(7, 4),
300 GPIO2D5_UART5_TX_M2 = 10,
301 };
302
303 /* GPIO3A_IOMUX_SEL_H */
304 enum {
305 GPIO3A2_SHIFT = 8,
306 GPIO3A2_MASK = GENMASK(11, 8),
307 GPIO3A2_UART8_TX_M1 = 10,
308
309 GPIO3A3_SHIFT = 12,
310 GPIO3A3_MASK = GENMASK(15, 12),
311 GPIO3A3_UART8_RX_M1 = 10,
312 };
313
314 /* GPIO3B_IOMUX_SEL_L */
315 enum {
316 GPIO3B1_SHIFT = 4,
317 GPIO3B1_MASK = GENMASK(7, 4),
318 GPIO3B1_UART2_TX_M2 = 10,
319
320 GPIO3B2_SHIFT = 8,
321 GPIO3B2_MASK = GENMASK(11, 8),
322 GPIO3B2_UART2_RX_M2 = 10,
323 };
324
325 /* GPIO3B_IOMUX_SEL_H */
326 enum {
327 GPIO3B5_SHIFT = 4,
328 GPIO3B5_MASK = GENMASK(7, 4),
329 GPIO3B5_UART3_TX_M1 = 10,
330
331 GPIO3B6_SHIFT = 8,
332 GPIO3B6_MASK = GENMASK(11, 8),
333 GPIO3B6_UART3_RX_M1 = 10,
334 };
335
336 /* GPIO3C_IOMUX_SEL_L */
337 enum {
338 GPIO3C0_SHIFT = 0,
339 GPIO3C0_MASK = GENMASK(3, 0),
340 GPIO3C0_UART7_TX_M1 = 10,
341
342 GPIO3C1_SHIFT = 4,
343 GPIO3C1_MASK = GENMASK(7, 4),
344 GPIO3C1_UART7_RX_M1 = 10,
345 };
346
347 /* GPIO3C_IOMUX_SEL_H */
348 enum {
349 GPIO3C4_SHIFT = 0,
350 GPIO3C4_MASK = GENMASK(3, 0),
351 GPIO3C4_UART5_TX_M1 = 10,
352
353 GPIO3C5_SHIFT = 4,
354 GPIO3C5_MASK = GENMASK(7, 4),
355 GPIO3C5_UART5_RX_M1 = 10,
356 };
357
358 /* GPIO3D_IOMUX_SEL_L */
359 enum {
360 GPIO3D0_SHIFT = 0,
361 GPIO3D0_MASK = GENMASK(3, 0),
362 GPIO3D0_UART4_RX_M1 = 10,
363
364 GPIO3D1_SHIFT = 4,
365 GPIO3D1_MASK = GENMASK(7, 4),
366 GPIO3D1_UART4_TX_M1 = 10,
367 };
368
369 /* GPIO3D_IOMUX_SEL_H */
370 enum {
371 GPIO3D4_SHIFT = 0,
372 GPIO3D4_MASK = GENMASK(3, 0),
373 GPIO3D4_UART9_RX_M2 = 10,
374
375 GPIO3D5_SHIFT = 4,
376 GPIO3D5_MASK = GENMASK(7, 4),
377 GPIO3D5_UART9_TX_M2 = 10,
378 };
379
380 /* GPIO4A_IOMUX_SEL_L */
381 enum {
382 GPIO4A3_SHIFT = 12,
383 GPIO4A3_MASK = GENMASK(15, 12),
384 GPIO4A3_UART0_TX_M2 = 10,
385 };
386
387 /* GPIO4A_IOMUX_SEL_H */
388 enum {
389 GPIO4A4_SHIFT = 0,
390 GPIO4A4_MASK = GENMASK(3, 0),
391 GPIO4A4_UART0_RX_M2 = 10,
392
393 GPIO4A5_SHIFT = 4,
394 GPIO4A5_MASK = GENMASK(7, 4),
395 GPIO4A5_UART3_TX_M2 = 10,
396
397 GPIO4A6_SHIFT = 8,
398 GPIO4A6_MASK = GENMASK(11, 8),
399 GPIO4A6_UART3_RX_M2 = 10,
400 };
401
402 /* GPIO4B_IOMUX_SEL_L */
403 enum {
404 GPIO4B0_SHIFT = 0,
405 GPIO4B0_MASK = GENMASK(3, 0),
406 GPIO4B0_UART8_TX_M0 = 10,
407
408 GPIO4B1_SHIFT = 4,
409 GPIO4B1_MASK = GENMASK(7, 4),
410 GPIO4B1_UART8_RX_M0 = 10,
411 };
412
413 /* GPIO4B_IOMUX_SEL_H */
414 enum {
415 GPIO4B4_SHIFT = 0,
416 GPIO4B4_MASK = GENMASK(3, 0),
417 GPIO4B4_UART9_TX_M1 = 10,
418
419 GPIO4B5_SHIFT = 4,
420 GPIO4B5_MASK = GENMASK(7, 4),
421 GPIO4B5_UART9_RX_M1 = 10,
422 };
423
424 /* GPIO4D_IOMUX_SEL_L */
425 enum {
426 GPIO4D0_SHIFT = 0,
427 GPIO4D0_MASK = GENMASK(3, 0),
428 GPIO4D0_GPIO = 0,
429 GPIO4D0_SDMMC_D0 = 1,
430 GPIO4D0_PDM1_SDI3_M0 = 2,
431 GPIO4D0_JTAG_TCK_M1 = 5,
432 GPIO4D0_I2C3_SCL_M4 = 9,
433 GPIO4D0_UART2_TX_M1 = 10,
434 GPIO4D0_PWM8_M1 = 12,
435
436 GPIO4D1_SHIFT = 4,
437 GPIO4D1_MASK = GENMASK(7, 4),
438 GPIO4D1_GPIO = 0,
439 GPIO4D1_SDMMC_D1 = 1,
440 GPIO4D1_PDM1_SDI2_M0 = 2,
441 GPIO4D1_JTAG_TMS_M1 = 5,
442 GPIO4D1_I2C3_SDA_M4 = 9,
443 GPIO4D1_UART2_RX_M1 = 10,
444 GPIO4D1_PWM9_M1 = 12,
445 };
446
447 /* GPIO4D_IOMUX_SEL_H */
448 enum {
449 GPIO4D4_SHIFT = 0,
450 GPIO4D4_MASK = GENMASK(3, 0),
451 GPIO4D4_UART5_RX_M0 = 10,
452
453 GPIO4D5_SHIFT = 4,
454 GPIO4D5_MASK = GENMASK(7, 4),
455 GPIO4D5_UART5_TX_M0 = 10,
456 };
457
board_debug_uart_init(void)458 void board_debug_uart_init(void)
459 {
460 __maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
461
462 /* UART 0 */
463 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfd890000)
464
465 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
466 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
467 static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
468
469 /* UART0_M0 Switch iomux */
470 rk_clrsetreg(&pmu2_ioc->gpio0c_iomux_sel_h,
471 GPIO0C4_MASK | GPIO0C5_MASK,
472 GPIO0C4_UART0_RX_M0 << GPIO0C4_SHIFT |
473 GPIO0C5_UART0_TX_M0 << GPIO0C5_SHIFT);
474
475 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
476 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
477 static struct rk3588_pmu1_ioc * const pmu1_ioc = (void *)PMU1_IOC_BASE;
478
479 /* UART0_M1 Switch iomux */
480 rk_clrsetreg(&pmu1_ioc->gpio0b_iomux_sel_l,
481 GPIO0B0_MASK | GPIO0B1_MASK,
482 GPIO0B0_UART0_RX_M1 << GPIO0B0_SHIFT |
483 GPIO0B1_UART0_TX_M1 << GPIO0B1_SHIFT);
484
485 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
486 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
487
488 /* UART0_M2 Switch iomux */
489 rk_clrsetreg(&bus_ioc->gpio4a_iomux_sel_h,
490 GPIO4A4_MASK,
491 GPIO4A4_UART0_RX_M2 << GPIO4A4_SHIFT);
492 rk_clrsetreg(&bus_ioc->gpio4a_iomux_sel_l,
493 GPIO4A3_MASK,
494 GPIO4A3_UART0_TX_M2 << GPIO4A3_SHIFT);
495
496 #endif
497
498 /* UART 1 */
499 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb40000)
500 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
501 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
502
503 /* UART1_M0 Switch iomux */
504 rk_clrsetreg(&bus_ioc->gpio2b_iomux_sel_h,
505 GPIO2B6_MASK | GPIO2B7_MASK,
506 GPIO2B6_UART1_RX_M0 << GPIO2B6_SHIFT |
507 GPIO2B7_UART1_TX_M0 << GPIO2B7_SHIFT);
508
509 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
510 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
511
512 /* UART1_M1 Switch iomux */
513 rk_clrsetreg(&bus_ioc->gpio1b_iomux_sel_h,
514 GPIO1B7_MASK | GPIO1B6_MASK,
515 GPIO1B7_UART1_RX_M1 << GPIO1B7_SHIFT |
516 GPIO1B6_UART1_TX_M1 << GPIO1B6_SHIFT);
517
518 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
519 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
520
521 static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
522
523 /* Refer to BUS_IOC */
524 rk_clrsetreg(&pmu2_ioc->gpio0d_iomux_sel_l,
525 GPIO0D2_MASK | GPIO0D1_MASK,
526 GPIO0D2_REFER << GPIO0D2_SHIFT |
527 GPIO0D1_REFER << GPIO0D1_SHIFT);
528
529 /* UART1_M2 Switch iomux */
530 rk_clrsetreg(&bus_ioc->gpio0d_iomux_sel_l,
531 GPIO0D2_MASK | GPIO0D1_MASK,
532 GPIO0D2_UART1_RX_M2 << GPIO0D2_SHIFT |
533 GPIO0D1_UART1_TX_M2 << GPIO0D1_SHIFT);
534
535 #endif
536
537 /* UART 2 */
538 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb50000)
539 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
540 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
541
542 static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
543
544 /* Refer to BUS_IOC */
545 rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
546 GPIO0B6_MASK | GPIO0B5_MASK,
547 GPIO0B6_REFER << GPIO0B6_SHIFT |
548 GPIO0B5_REFER << GPIO0B5_SHIFT);
549
550 /* UART2_M0 Switch iomux */
551 rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
552 GPIO0B6_MASK | GPIO0B5_MASK,
553 GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
554 GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
555
556 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
557 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
558
559 /* UART2_M1 Switch iomux */
560 rk_clrsetreg(&bus_ioc->gpio4d_iomux_sel_l,
561 GPIO4D1_MASK | GPIO4D0_MASK,
562 GPIO4D1_UART2_RX_M1 << GPIO4D1_SHIFT |
563 GPIO4D0_UART2_TX_M1 << GPIO4D0_SHIFT);
564
565 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
566 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
567
568 /* UART2_M2 Switch iomux */
569 rk_clrsetreg(&bus_ioc->gpio3b_iomux_sel_l,
570 GPIO3B2_MASK | GPIO3B1_MASK,
571 GPIO3B2_UART2_RX_M2 << GPIO3B2_SHIFT |
572 GPIO3B1_UART2_TX_M2 << GPIO3B1_SHIFT);
573
574 #endif
575
576 /* UART 3 */
577 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb60000)
578 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
579 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
580
581 /* UART3_M0 Switch iomux */
582 rk_clrsetreg(&bus_ioc->gpio1c_iomux_sel_l,
583 GPIO1C0_MASK | GPIO1C1_MASK,
584 GPIO1C0_UART3_RX_M0 << GPIO1C0_SHIFT |
585 GPIO1C1_UART3_TX_M0 << GPIO1C1_SHIFT);
586
587 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
588 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
589
590 /* UART3_M1 Switch iomux */
591 rk_clrsetreg(&bus_ioc->gpio3b_iomux_sel_h,
592 GPIO3B6_MASK | GPIO3B5_MASK,
593 GPIO3B6_UART3_RX_M1 << GPIO3B6_SHIFT |
594 GPIO3B5_UART3_TX_M1 << GPIO3B5_SHIFT);
595
596 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
597 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
598
599 /* UART3_M2 Switch iomux */
600 rk_clrsetreg(&bus_ioc->gpio4a_iomux_sel_h,
601 GPIO4A6_MASK | GPIO4A5_MASK,
602 GPIO4A6_UART3_RX_M2 << GPIO4A6_SHIFT |
603 GPIO4A5_UART3_TX_M2 << GPIO4A5_SHIFT);
604
605 #endif
606
607 /* UART 4 */
608 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb70000)
609 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
610 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
611
612 /* UART4_M0 Switch iomux */
613 rk_clrsetreg(&bus_ioc->gpio1d_iomux_sel_l,
614 GPIO1D3_MASK | GPIO1D2_MASK,
615 GPIO1D3_UART4_RX_M0 << GPIO1D3_SHIFT |
616 GPIO1D2_UART4_TX_M0 << GPIO1D2_SHIFT);
617
618 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
619 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
620
621 /* UART4_M1 Switch iomux */
622 rk_clrsetreg(&bus_ioc->gpio3d_iomux_sel_l,
623 GPIO3D0_MASK | GPIO3D1_MASK,
624 GPIO3D0_UART4_RX_M1 << GPIO3D0_SHIFT |
625 GPIO3D1_UART4_TX_M1 << GPIO3D1_SHIFT);
626
627 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
628 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
629
630 /* UART4_M2 Switch iomux */
631 rk_clrsetreg(&bus_ioc->gpio1b_iomux_sel_l,
632 GPIO1B2_MASK | GPIO1B3_MASK,
633 GPIO1B2_UART4_RX_M2 << GPIO1B2_SHIFT |
634 GPIO1B3_UART4_TX_M2 << GPIO1B3_SHIFT);
635
636 #endif
637
638 /* UART 5 */
639 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb80000)
640 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
641 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
642
643 /* UART5_M0 Switch iomux */
644 rk_clrsetreg(&bus_ioc->gpio4d_iomux_sel_h,
645 GPIO4D4_MASK | GPIO4D5_MASK,
646 GPIO4D4_UART5_RX_M0 << GPIO4D4_SHIFT |
647 GPIO4D5_UART5_TX_M0 << GPIO4D5_SHIFT);
648
649 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
650 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
651
652 /* UART5_M1 Switch iomux */
653 rk_clrsetreg(&bus_ioc->gpio3c_iomux_sel_h,
654 GPIO3C5_MASK | GPIO3C4_MASK,
655 GPIO3C5_UART5_RX_M1 << GPIO3C5_SHIFT |
656 GPIO3C4_UART5_TX_M1 << GPIO3C4_SHIFT);
657
658 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
659 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
660
661 /* UART5_M2 Switch iomux */
662 rk_clrsetreg(&bus_ioc->gpio2d_iomux_sel_h,
663 GPIO2D4_MASK | GPIO2D5_MASK,
664 GPIO2D4_UART5_RX_M2 << GPIO2D4_SHIFT |
665 GPIO2D5_UART5_TX_M2 << GPIO2D5_SHIFT);
666
667 #endif
668
669 /* UART 6 */
670 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb90000)
671 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
672 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
673
674 /* UART6_M0 Switch iomux */
675 rk_clrsetreg(&bus_ioc->gpio2a_iomux_sel_h,
676 GPIO2A6_MASK | GPIO2A7_MASK,
677 GPIO2A6_UART6_RX_M0 << GPIO2A6_SHIFT |
678 GPIO2A7_UART6_TX_M0 << GPIO2A7_SHIFT);
679
680 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
681 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
682
683 /* UART6_M1 Switch iomux */
684 rk_clrsetreg(&bus_ioc->gpio1a_iomux_sel_l,
685 GPIO1A0_MASK | GPIO1A1_MASK,
686 GPIO1A0_UART6_RX_M1 << GPIO1A0_SHIFT |
687 GPIO1A1_UART6_TX_M1 << GPIO1A1_SHIFT);
688
689 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
690 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
691
692 /* UART6_M2 Switch iomux */
693 rk_clrsetreg(&bus_ioc->gpio1d_iomux_sel_l,
694 GPIO1D1_MASK | GPIO1D0_MASK,
695 GPIO1D1_UART6_RX_M2 << GPIO1D1_SHIFT |
696 GPIO1D0_UART6_TX_M2 << GPIO1D0_SHIFT);
697
698 #endif
699
700 /* UART 7 */
701 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeba0000)
702 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
703 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
704
705 /* UART7_M0 Switch iomux */
706 rk_clrsetreg(&bus_ioc->gpio2b_iomux_sel_h,
707 GPIO2B4_MASK | GPIO2B5_MASK,
708 GPIO2B4_UART7_RX_M0 << GPIO2B4_SHIFT |
709 GPIO2B5_UART7_TX_M0 << GPIO2B5_SHIFT);
710
711 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
712 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
713
714 /* UART7_M1 Switch iomux */
715 rk_clrsetreg(&bus_ioc->gpio3c_iomux_sel_l,
716 GPIO3C1_MASK | GPIO3C0_MASK,
717 GPIO3C1_UART7_RX_M1 << GPIO3C1_SHIFT |
718 GPIO3C0_UART7_TX_M1 << GPIO3C0_SHIFT);
719
720 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
721 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
722
723 /* UART7_M2 Switch iomux */
724 rk_clrsetreg(&bus_ioc->gpio1b_iomux_sel_h,
725 GPIO1B4_MASK | GPIO1B5_MASK,
726 GPIO1B4_UART7_RX_M2 << GPIO1B4_SHIFT |
727 GPIO1B5_UART7_TX_M2 << GPIO1B5_SHIFT);
728
729 #endif
730
731 /* UART 8 */
732 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfebb0000)
733 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
734 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
735
736 /* UART8_M0 Switch iomux */
737 rk_clrsetreg(&bus_ioc->gpio4b_iomux_sel_l,
738 GPIO4B1_MASK | GPIO4B0_MASK,
739 GPIO4B1_UART8_RX_M0 << GPIO4B1_SHIFT |
740 GPIO4B0_UART8_TX_M0 << GPIO4B0_SHIFT);
741
742 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
743 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
744
745 /* UART8_M1 Switch iomux */
746 rk_clrsetreg(&bus_ioc->gpio3a_iomux_sel_l,
747 GPIO3A3_MASK | GPIO3A2_MASK,
748 GPIO3A3_UART8_RX_M1 << GPIO3A3_SHIFT |
749 GPIO3A2_UART8_TX_M1 << GPIO3A2_SHIFT);
750
751 #endif
752
753 /* UART 9 */
754 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfebc0000)
755 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
756 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
757
758 /* UART9_M0 Switch iomux */
759 rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_h,
760 GPIO2C4_MASK,
761 GPIO2C4_UART9_RX_M0 << GPIO2C4_SHIFT);
762
763 /* UART9_M0 Switch iomux */
764 rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l,
765 GPIO2C2_MASK,
766 GPIO2C2_UART9_TX_M0 << GPIO2C2_SHIFT);
767
768 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
769 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
770
771 /* UART9_M1 Switch iomux */
772 rk_clrsetreg(&bus_ioc->gpio4b_iomux_sel_h,
773 GPIO4B5_MASK | GPIO4B4_MASK,
774 GPIO4B5_UART9_RX_M1 << GPIO4B5_SHIFT |
775 GPIO4B4_UART9_TX_M1 << GPIO4B4_SHIFT);
776
777 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
778 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
779
780 /* UART9_M2 Switch iomux */
781 rk_clrsetreg(&bus_ioc->gpio3d_iomux_sel_h,
782 GPIO3D4_MASK | GPIO3D5_MASK,
783 GPIO3D4_UART9_RX_M2 << GPIO3D4_SHIFT |
784 GPIO3D5_UART9_TX_M2 << GPIO3D5_SHIFT);
785
786 #endif
787
788 #endif
789 }
790
791 #ifdef CONFIG_SPL_BUILD
rockchip_stimer_init(void)792 void rockchip_stimer_init(void)
793 {
794 /* If Timer already enabled, don't re-init it */
795 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
796
797 if (reg & 0x1)
798 return;
799
800 asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
801 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
802 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
803 writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
804 }
805
806 static u32 gpio4d_iomux_sel_l = 0xffffffff;
807 static u32 gpio4d_iomux_sel_h;
808 static u32 gpio0a_iomux_sel_h;
809
spl_board_sd_iomux_save(void)810 void spl_board_sd_iomux_save(void)
811 {
812 struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
813 struct rk3588_pmu1_ioc * const pmu1_ioc = (void *)PMU1_IOC_BASE;
814
815 gpio4d_iomux_sel_l = readl(&bus_ioc->gpio4d_iomux_sel_l);
816 gpio4d_iomux_sel_h = readl(&bus_ioc->gpio4d_iomux_sel_h);
817 gpio0a_iomux_sel_h = readl(&pmu1_ioc->gpio0a_iomux_sel_h);
818 }
819
spl_board_storages_fixup(struct spl_image_loader * loader)820 void spl_board_storages_fixup(struct spl_image_loader *loader)
821 {
822 int ret = 0;
823
824 if (!loader)
825 return;
826
827 if (loader->boot_device == BOOT_DEVICE_MMC2 && gpio4d_iomux_sel_l != 0xffffffff) {
828 struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
829 struct rk3588_pmu1_ioc * const pmu1_ioc = (void *)PMU1_IOC_BASE;
830 struct mmc *mmc = NULL;
831 bool no_card;
832
833 ret = spl_mmc_find_device(&mmc, BOOT_DEVICE_MMC2);
834 if (ret)
835 return;
836
837 no_card = mmc_getcd(mmc) == 0;
838 if (no_card) {
839 writel(0xffffuL << 16 | gpio4d_iomux_sel_l, &bus_ioc->gpio4d_iomux_sel_l);
840 writel(0xffffuL << 16 | gpio4d_iomux_sel_h, &bus_ioc->gpio4d_iomux_sel_h);
841 writel(0xffffuL << 16 | gpio0a_iomux_sel_h, &pmu1_ioc->gpio0a_iomux_sel_h);
842 }
843 }
844 }
845 #endif
846
847 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)848 int arch_cpu_init(void)
849 {
850 #ifdef CONFIG_SPL_BUILD
851 int secure_reg;
852
853 /* Set the SDMMC eMMC crypto_ns FSPI access secure area */
854 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
855 secure_reg &= 0xffff;
856 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
857 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
858 secure_reg &= 0xffff;
859 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
860 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
861 secure_reg &= 0xffff;
862 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
863 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
864 secure_reg &= 0xffff;
865 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
866 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
867 secure_reg &= 0xffff0000;
868 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
869
870 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
871 secure_reg &= 0xffff;
872 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
873 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
874 secure_reg &= 0xffff;
875 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
876 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
877 secure_reg &= 0xffff;
878 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
879 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
880 secure_reg &= 0xffff;
881 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
882 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
883 secure_reg &= 0xffff0000;
884 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
885
886 /*
887 * Select clk_tx source as default for i2s2/i2s3
888 * Set I2Sx_MCLK as input default
889 *
890 * It's safe to set mclk as input default to avoid high freq glitch
891 * which may make devices work unexpected. And then enabled by
892 * kernel stage or any state where user use it.
893 */
894 writel(0x03c703c7, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
895
896 if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x2222) {
897 /* Set the fspi m0 io ds level to 55ohm */
898 writel(0x00070002, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
899 writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
900 writel(0x07000200, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
901 } else if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x1111) {
902 /*
903 * set the emmc io drive strength:
904 * data and cmd: 50ohm
905 * clock: 25ohm
906 */
907 writel(0x00770052, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
908 writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
909 writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
910 } else if ((readl(BUS_IOC_BASE + BUS_IOC_GPIO2B_IOMUX_SEL_L) & 0xf0ff) == 0x3033) {
911 /* Set the fspi m1 io ds level to 55ohm */
912 writel(0x33002200, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2A_DS_H);
913 writel(0x30332022, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_L);
914 writel(0x00030002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_H);
915 } else if (readl(BUS_IOC_BASE + BUS_IOC_GPIO3A_IOMUX_SEL_L) == 0x5555) {
916 /* Set the fspi m2 io ds level to 55ohm */
917 writel(0x77772222, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_L);
918 writel(0x00700020, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_H);
919 writel(0x00070002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3C_DS_H);
920 }
921
922 /*
923 * Assert reset the pipephy0, pipephy1 and pipephy2,
924 * and de-assert reset them in Kernel combphy driver.
925 */
926 writel(0x01c001c0, CRU_BASE + CRU_SOFTRST_CON77);
927
928 /*
929 * Assert SIDDQ for USB 2.0 PHY1, PHY2 and PHY3 to
930 * power down all analog block to save power. And
931 * PHY0 for OTG0 interface still in normal mode.
932 */
933 writel(0x20002000, USB2PHY1_GRF_BASE + USB2PHY_GRF_CON2);
934 writel(0x20002000, USB2PHY2_GRF_BASE + USB2PHY_GRF_CON2);
935 writel(0x20002000, USB2PHY3_GRF_BASE + USB2PHY_GRF_CON2);
936
937 /* Assert hdptxphy init,cmn,lane reset */
938 writel(0xb800b800, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON03);
939 writel(0x00030003, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON04);
940
941 spl_board_sd_iomux_save();
942 #else /* U-Boot */
943 /* uboot: config iomux */
944 #ifdef CONFIG_ROCKCHIP_EMMC_IOMUX
945 /* Set emmc iomux for good extention if the emmc is not the boot device */
946 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);
947 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
948 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
949 #endif
950 /*
951 * set VOP M0 and VOP M1 to priority 0x303,then
952 * Peri > VOP/MCU > ISP/VICAP > other
953 * Note: VOP priority can only be modified during the u-boot stage,
954 * as VOP default power down, and power up after trust.
955 */
956 writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M0_PRIORITY_REG);
957 writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M1_PRIORITY_REG);
958 #endif
959
960 /* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */
961 writel(0x00080008, USBGRF_BASE + USB_GRF_USB3OTG0_CON1);
962
963 return 0;
964 }
965 #endif
966
967 #define BAD_CPU(mask, n) ((mask) & (1 << (n)))
968 #define BAD_RKVENC(mask, n) ((mask) & (1 << (n)))
969
fdt_rm_path(void * blob,const char * path)970 static void fdt_rm_path(void *blob, const char *path)
971 {
972 fdt_del_node(blob, fdt_path_offset(blob, path));
973 }
974
fdt_rm_cooling_map(const void * blob,u8 cpu_mask)975 static void fdt_rm_cooling_map(const void *blob, u8 cpu_mask)
976 {
977 int map1, map2;
978 int cpub1_phd;
979 int cpub3_phd;
980 int node;
981 u32 *pp;
982
983 node = fdt_path_offset(blob, "/cpus/cpu@500");
984 cpub1_phd = fdtdec_get_uint(blob, node, "phandle", -1);
985 node = fdt_path_offset(blob, "/cpus/cpu@700");
986 cpub3_phd = fdtdec_get_uint(blob, node, "phandle", -1);
987
988 if (BAD_CPU(cpu_mask, 4)) {
989 map1 = fdt_path_offset(blob, "/thermal-zones/soc-thermal/cooling-maps/map1");
990 if (map1 > 0) {
991 if (BAD_CPU(cpu_mask, 5)) {
992 debug("rm: cooling-device map1\n");
993 fdt_del_node((void *)blob, map1);
994 } else {
995 pp = (u32 *)fdt_getprop(blob, map1, "cooling-device", NULL);
996 if (pp) {
997 pp[0] = cpu_to_fdt32(cpub1_phd);
998 debug("fix: cooling-device cpub0->cpub1\n");
999 }
1000 }
1001 }
1002 }
1003
1004 if (BAD_CPU(cpu_mask, 6)) {
1005 map2 = fdt_path_offset(blob, "/thermal-zones/soc-thermal/cooling-maps/map2");
1006 if (map2 > 0) {
1007 if (BAD_CPU(cpu_mask, 7)) {
1008 debug("rm: cooling-device map2\n");
1009 fdt_del_node((void *)blob, map2);
1010 } else {
1011 pp = (u32 *)fdt_getprop(blob, map2, "cooling-device", NULL);
1012 if (pp) {
1013 pp[0] = cpu_to_fdt32(cpub3_phd);
1014 debug("fix: cooling-device cpub2->cpub3\n");
1015 }
1016 }
1017 }
1018 }
1019 }
1020
fdt_rm_cpu_affinity(const void * blob,u8 cpu_mask)1021 static void fdt_rm_cpu_affinity(const void *blob, u8 cpu_mask)
1022 {
1023 int i, remain, arm_pmu;
1024 u32 new_aff[8];
1025 u32 *aff;
1026
1027 arm_pmu = fdt_path_offset(blob, "/arm-pmu");
1028 if (arm_pmu > 0) {
1029 aff = (u32 *)fdt_getprop(blob, arm_pmu, "interrupt-affinity", NULL);
1030 if (!aff)
1031 return;
1032
1033 for (i = 0, remain = 0; i < 8; i++) {
1034 if (!BAD_CPU(cpu_mask, i)) {
1035 new_aff[remain++] = aff[i];
1036 debug("new_aff: 0x%08x\n", (u32)aff[i]);
1037 }
1038 }
1039
1040 fdt_setprop((void *)blob, arm_pmu, "interrupt-affinity", new_aff, remain * 4);
1041 }
1042 }
1043
fdt_rm_cpu(const void * blob,u8 cpu_mask)1044 static void fdt_rm_cpu(const void *blob, u8 cpu_mask)
1045 {
1046 const char *cpu_node_name[] = {
1047 "cpu@0", "cpu@100", "cpu@200", "cpu@300",
1048 "cpu@400", "cpu@500", "cpu@600", "cpu@700",
1049 };
1050 const char *cluster_core_name[] = {
1051 "core0", "core1", "core2", "core3",
1052 "core0", "core1", "core0", "core1",
1053 };
1054 const char *cluster_core, *cpu_node;
1055 int root_cpus, cpu;
1056 int cluster;
1057 int i;
1058
1059 root_cpus = fdt_path_offset(blob, "/cpus");
1060 if (root_cpus < 0)
1061 return;
1062
1063 for (i = 0; i < 8; i++) {
1064 if (!BAD_CPU(cpu_mask, i))
1065 continue;
1066
1067 if (i < 4)
1068 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster0");
1069 else if (i < 6)
1070 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster1");
1071 else
1072 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster2");
1073
1074 if (cluster < 0)
1075 return;
1076
1077 cpu_node = cpu_node_name[i];
1078 cluster_core = cluster_core_name[i];
1079 debug("rm: %s, %s\n", cpu_node, cluster_core);
1080
1081 cpu = fdt_subnode_offset(blob, cluster, cluster_core);
1082 if (cpu > 0)
1083 fdt_del_node((void *)blob, cpu);
1084
1085 cpu = fdt_subnode_offset(blob, root_cpus, cpu_node);
1086 if (cpu > 0)
1087 fdt_del_node((void *)blob, cpu);
1088 }
1089
1090 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster1");
1091 if (BAD_CPU(cpu_mask, 4) && BAD_CPU(cpu_mask, 5)) {
1092 debug("rm: cpu cluster1\n");
1093 fdt_del_node((void *)blob, cluster);
1094 }
1095
1096 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster2");
1097 if (BAD_CPU(cpu_mask, 6) && BAD_CPU(cpu_mask, 7)) {
1098 debug("rm: cpu cluster2\n");
1099 fdt_del_node((void *)blob, cluster);
1100 } else {
1101 /* rename, otherwise linux only handles cluster0 */
1102 if (fdt_path_offset(blob, "/cpus/cpu-map/cluster1") < 0)
1103 fdt_set_name((void *)blob, cluster, "cluster1");
1104 }
1105 }
1106
fdt_rm_cpus(const void * blob,u8 cpu_mask)1107 static void fdt_rm_cpus(const void *blob, u8 cpu_mask)
1108 {
1109 /*
1110 * policy:
1111 *
1112 * 1. both of cores within the same cluster should be normal, otherwise
1113 * remove both of them.
1114 * 2. if core4~7 are all normal, remove core6 and core7 anyway.
1115 */
1116 if (BAD_CPU(cpu_mask, 4) || BAD_CPU(cpu_mask, 5))
1117 cpu_mask |= BIT(4) | BIT(5);
1118 if (BAD_CPU(cpu_mask, 6) || BAD_CPU(cpu_mask, 7))
1119 cpu_mask |= BIT(6) | BIT(7);
1120
1121 if (!BAD_CPU(cpu_mask, 4) & !BAD_CPU(cpu_mask, 5) &&
1122 !BAD_CPU(cpu_mask, 6) & !BAD_CPU(cpu_mask, 7))
1123 cpu_mask |= BIT(6) | BIT(7);
1124
1125 fdt_rm_cooling_map(blob, cpu_mask);
1126 fdt_rm_cpu_affinity(blob, cpu_mask);
1127 fdt_rm_cpu(blob, cpu_mask);
1128 }
1129
fdt_rm_gpu(void * blob)1130 static void fdt_rm_gpu(void *blob)
1131 {
1132 /*
1133 * policy:
1134 *
1135 * Remove GPU by default.
1136 */
1137 fdt_rm_path(blob, "/gpu@fb000000");
1138 fdt_rm_path(blob, "/thermal-zones/soc-thermal/cooling-maps/map3");
1139 debug("rm: gpu\n");
1140 }
1141
fdt_rm_rkvdec01(void * blob)1142 static void fdt_rm_rkvdec01(void *blob)
1143 {
1144 /*
1145 * policy:
1146 *
1147 * Remove rkvdec0 and rkvdec1 by default.
1148 */
1149 fdt_rm_path(blob, "/rkvdec-core@fdc38000");
1150 fdt_rm_path(blob, "/iommu@fdc38700");
1151 fdt_rm_path(blob, "/rkvdec-core@fdc48000");
1152 fdt_rm_path(blob, "/iommu@fdc48700");
1153 debug("rm: rkvdec0, rkvdec1\n");
1154 }
1155
fdt_rm_rkvenc01(void * blob,u8 mask)1156 static void fdt_rm_rkvenc01(void *blob, u8 mask)
1157 {
1158 /*
1159 * policy:
1160 *
1161 * 1. remove bad.
1162 * 2. if both of rkvenc0 and rkvenc1 are normal, remove rkvenc1 by default.
1163 */
1164 if (!BAD_RKVENC(mask, 0) && !BAD_RKVENC(mask, 1)) {
1165 /* rkvenc1 */
1166 fdt_rm_path(blob, "/rkvenc-core@fdbe0000");
1167 fdt_rm_path(blob, "/iommu@fdbef000");
1168 debug("rm: rkvenv1\n");
1169 } else {
1170 if (BAD_RKVENC(mask, 0)) {
1171 fdt_rm_path(blob, "/rkvenc-core@fdbd0000");
1172 fdt_rm_path(blob, "/iommu@fdbdf000");
1173 debug("rm: rkvenv0\n");
1174
1175 }
1176 if (BAD_RKVENC(mask, 1)) {
1177 fdt_rm_path(blob, "/rkvenc-core@fdbe0000");
1178 fdt_rm_path(blob, "/iommu@fdbef000");
1179 debug("rm: rkvenv1\n");
1180 }
1181 }
1182 }
1183
1184 #define CHIP_ID_OFF 2
1185 #define IP_STATE_OFF 29
1186
fdt_fixup_modules(void * blob)1187 static int fdt_fixup_modules(void *blob)
1188 {
1189 struct udevice *dev;
1190 u8 ip_state[3];
1191 u8 chip_id[2];
1192 u8 rkvenc_mask;
1193 u8 cpu_mask;
1194 int ret;
1195
1196 ret = uclass_get_device_by_driver(UCLASS_MISC,
1197 DM_GET_DRIVER(rockchip_otp), &dev);
1198 if (ret) {
1199 printf("can't get otp device, ret=%d\n", ret);
1200 return ret;
1201 }
1202
1203 ret = misc_read(dev, CHIP_ID_OFF, &chip_id, sizeof(chip_id));
1204 if (ret) {
1205 printf("can't read chip id, ret=%d\n", ret);
1206 return ret;
1207 }
1208
1209 debug("# chip: rk%02x%02x\n", chip_id[0], chip_id[1]);
1210
1211 /* only rk3582 goes further */
1212 if (!(chip_id[0] == 0x35 && chip_id[1] == 0x82))
1213 return 0;
1214
1215 ret = misc_read(dev, IP_STATE_OFF, &ip_state, sizeof(ip_state));
1216 if (ret) {
1217 printf("can't read ip state, ret=%d\n", ret);
1218 return ret;
1219 }
1220
1221 /* ip_state[0]: bit0~7 */
1222 cpu_mask = ip_state[0];
1223 /* ip_state[2]: bit0,2 */
1224 rkvenc_mask = (ip_state[2] & 0x1) | ((ip_state[2] & 0x4) >> 1);
1225 #if 0
1226 /* ip_state[1]: bit1~4 */
1227 gpu_mask = (ip_state[1] & 0x1e) >> 1;
1228 /* ip_state[1]: bit6,7 */
1229 rkvdec_mask = (ip_state[1] & 0xc0) >> 6;
1230 #endif
1231
1232 debug("hwmask: 0x%02x, 0x%02x, 0x%02x\n", ip_state[0], ip_state[1], ip_state[2]);
1233 debug("swmask: 0x%02x, 0x%02x\n", cpu_mask, rkvenc_mask);
1234
1235 /*
1236 * RK3582 Policy: gpu/rkvdec are removed by default, the same for other
1237 * IP under some condition.
1238 *
1239 * So don't use pattern like "if (rkvenc_mask) then fdt_rm_rkvenc01()",
1240 * just go through all of them as this chip is rk3582.
1241 *
1242 * FIXUP WARNING!
1243 *
1244 * The node delete changes the fdt structure, a node offset you already
1245 * got before maybe not right by now. Make sure always reading the node
1246 * offset exactly before you are going to use.
1247 */
1248 fdt_rm_gpu(blob);
1249 fdt_rm_rkvdec01(blob);
1250 fdt_rm_rkvenc01(blob, rkvenc_mask);
1251 fdt_rm_cpus(blob, cpu_mask);
1252
1253 return 0;
1254 }
1255
rk_board_dm_fdt_fixup(const void * blob)1256 int rk_board_dm_fdt_fixup(const void *blob)
1257 {
1258 return fdt_fixup_modules((void *)blob);
1259 }
1260
rk_board_fdt_fixup(const void * blob)1261 int rk_board_fdt_fixup(const void *blob)
1262 {
1263 int node;
1264
1265 /* set hdmirx to low power mode */
1266 node = fdt_path_offset(blob, HDMIRX_NODE_FDT_PATH);
1267 if (node >= 0) {
1268 if (fdtdec_get_int(blob, node, "low-power-mode", 0)) {
1269 printf("hdmirx low power mode\n");
1270 writel(0x00000100, RK3588_PHY_CONFIG);
1271 }
1272 }
1273
1274 return 0;
1275 }
1276
1277 #ifdef CONFIG_SPL_BUILD
spl_fit_standalone_release(char * id,uintptr_t entry_point)1278 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
1279 {
1280 u32 val;
1281
1282 /* pmu m0 configuration: */
1283 /* set gpll */
1284 writel(0x00f00042, CRU_BASE + CRU_GPLL_CON1);
1285 /* set pmu mcu to access ddr memory */
1286 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
1287 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
1288 /* set pmu mcu to access system memory */
1289 val = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
1290 writel(val & 0x000000ff, FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
1291 /* set pmu mcu to secure */
1292 writel(0x00080000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON0);
1293 /* set start addr, pmu_mcu_code_addr_start */
1294 writel(0xFFFF0000 | (entry_point >> 16), PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON9);
1295 /* set pmu_mcu_sram_addr_start */
1296 writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON10);
1297 /* set pmu_mcu_tcm_addr_start */
1298 writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON13);
1299 /* set cache cache_peripheral_addr */
1300 /* 0xf0000000 ~ 0xfee00000 */
1301 writel(0xffff0000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON6);
1302 writel(0xffffee00, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON7);
1303 writel(0x00ff00ff, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON8);
1304 /* enable PMU WDT reset system */
1305 writel(0x02000200, BUS_SGRF_BASE + BUS_SGRF_SOC_CON2);
1306 /* select WDT trigger global reset. */
1307 writel(0x08400840, CRU_BASE + CRU_GLB_RST_CON);
1308 /* release pmu mcu */
1309 /* writel(0x20000000, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON00); */
1310
1311 return 0;
1312 }
1313 #endif
1314