Searched +full:0 +full:xc9410000 (Results 1 – 7 of 7) sorted by relevance
10 #define GXBB_PERIPHS_BASE 0xc883440011 #define GXBB_HIU_BASE 0xc883c00012 #define GXBB_ETH_BASE 0xc941000017 /* GPIO registers 0 to 6 */18 #define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))19 #define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)23 #define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)24 #define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)26 #define GXBB_ETH_REG_0_PHY_INTF BIT(0)35 #define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40)[all …]
23 reg = <0x48 0x14>;29 reg = <0xc9410000 0x1000030 0xc1108140 0x8>;
22 reg = <0xc1100000 0x200000>;25 ranges = <0x0 0xc1100000 0x200000>;31 reg = <0x4000 0x400>;36 reg = <0x7c00 0x200>;41 reg = <0x8100 0x8>;46 reg = <0x84c0 0x18>;53 reg = <0x84dc 0x18>;60 reg = <0x8500 0x20>;63 #size-cells = <0>;69 reg = <0x8550 0x10>;[all …]
18 #size-cells = <0>;24 reg = <0x200>;35 reg = <0x201>;46 reg = <0x202>;57 reg = <0x203>;164 hwrom@0 {165 reg = <0x0 0x200000>;172 reg = <0xc8000000 0x8000>;175 ranges = <0x0 0xc8000000 0x8000>;179 reg = <0x400 0x20>;[all …]
66 nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.71 this property should be set to 0ns (which disables the TX clock78 - 080 default: 0129 reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
64 hwrom_reserved: hwrom@0 {65 reg = <0x0 0x0 0x0 0x1000000>;71 reg = <0x0 0x10000000 0x0 0x200000>;78 size = <0x0 0xbc00000>;79 alignment = <0x0 0x400000>;85 #address-cells = <0x2>;86 #size-cells = <0x0>;88 cpu0: cpu@0 {91 reg = <0x0 0x0>;94 clocks = <&scpi_dvfs 0>;[all …]
29 hwrom_reserved: hwrom@0 {30 reg = <0x0 0x0 0x0 0x1000000>;36 reg = <0x0 0x10000000 0x0 0x200000>;42 reg = <0x0 0x05000000 0x0 0x300000>;48 reg = <0x0 0x05300000 0x0 0x2000000>;55 size = <0x0 0x10000000>;56 alignment = <0x0 0x400000>;84 #address-cells = <0x2>;85 #size-cells = <0x0>;87 cpu0: cpu@0 {[all …]