Searched +full:0 +full:x600000000 (Results 1 – 4 of 4) sorted by relevance
48 #define CONFIG_SYS_TEXT_BASE 0x5000000049 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0)51 #define DRAM_RSV_SIZE 0x0800000054 #define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)55 #define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)56 #define PHYS_SDRAM_2 0x50000000057 #define PHYS_SDRAM_2_SIZE 0x40000000u58 #define PHYS_SDRAM_3 0x60000000059 #define PHYS_SDRAM_3_SIZE 0x40000000u60 #define PHYS_SDRAM_4 0x700000000[all …]
52 0x600000000 in all the Sparx5 variants.
77 "clz\t%0,%1\n\t" in __ilog2()89 if ((x = ~x) == 0) in au_ffz()124 #define MEM_SDMODE0 0xB4000800125 #define MEM_SDMODE1 0xB4000808126 #define MEM_SDMODE2 0xB4000810128 #define MEM_SDADDR0 0xB4000820129 #define MEM_SDADDR1 0xB4000828130 #define MEM_SDADDR2 0xB4000830132 #define MEM_SDCONFIGA 0xB4000840133 #define MEM_SDCONFIGB 0xB4000848[all …]
346 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; in intel_pstate_set_itmt_prio()438 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { in intel_pstate_init_acpi_perf_limits()439 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", in intel_pstate_init_acpi_perf_limits()458 cpu->acpi_perf_data.states[0].core_frequency = in intel_pstate_init_acpi_perf_limits()507 cpu = all_cpu_data[0]; in update_turbo_state()516 struct cpudata *cpu = all_cpu_data[0]; in min_perf_pct_min()520 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; in min_perf_pct_min()535 return (s16)(epb & 0x0f); in intel_pstate_get_epb()544 * When hwp_req_data is 0, means that caller didn't read in intel_pstate_get_epp()553 epp = (hwp_req_data >> 24) & 0xff; in intel_pstate_get_epp()[all …]