Lines Matching +full:0 +full:x600000000
77 "clz\t%0,%1\n\t" in __ilog2()
89 if ((x = ~x) == 0) in au_ffz()
124 #define MEM_SDMODE0 0xB4000800
125 #define MEM_SDMODE1 0xB4000808
126 #define MEM_SDMODE2 0xB4000810
128 #define MEM_SDADDR0 0xB4000820
129 #define MEM_SDADDR1 0xB4000828
130 #define MEM_SDADDR2 0xB4000830
132 #define MEM_SDCONFIGA 0xB4000840
133 #define MEM_SDCONFIGB 0xB4000848
134 #define MEM_SDPRECMD 0xB40008c0
135 #define MEM_SDAUTOREF 0xB40008c8
137 #define MEM_SDWRMD0 0xB4000880
138 #define MEM_SDWRMD1 0xB4000888
139 #define MEM_SDWRMD2 0xB4000890
143 #define MEM_SDMODE0 0xB4000000
144 #define MEM_SDMODE1 0xB4000004
145 #define MEM_SDMODE2 0xB4000008
147 #define MEM_SDADDR0 0xB400000C
148 #define MEM_SDADDR1 0xB4000010
149 #define MEM_SDADDR2 0xB4000014
151 #define MEM_SDREFCFG 0xB4000018
152 #define MEM_SDPRECMD 0xB400001C
153 #define MEM_SDAUTOREF 0xB4000020
155 #define MEM_SDWRMD0 0xB4000024
156 #define MEM_SDWRMD1 0xB4000028
157 #define MEM_SDWRMD2 0xB400002C
161 #define MEM_SDSLEEP 0xB4000030
162 #define MEM_SDSMCKE 0xB4000034
165 #define MEM_STCFG0 0xB4001000
166 #define MEM_STTIME0 0xB4001004
167 #define MEM_STADDR0 0xB4001008
169 #define MEM_STCFG1 0xB4001010
170 #define MEM_STTIME1 0xB4001014
171 #define MEM_STADDR1 0xB4001018
173 #define MEM_STCFG2 0xB4001020
174 #define MEM_STTIME2 0xB4001024
175 #define MEM_STADDR2 0xB4001028
177 #define MEM_STCFG3 0xB4001030
178 #define MEM_STTIME3 0xB4001034
179 #define MEM_STADDR3 0xB4001038
181 /* Interrupt Controller 0 */
182 #define IC0_CFG0RD 0xB0400040
183 #define IC0_CFG0SET 0xB0400040
184 #define IC0_CFG0CLR 0xB0400044
186 #define IC0_CFG1RD 0xB0400048
187 #define IC0_CFG1SET 0xB0400048
188 #define IC0_CFG1CLR 0xB040004C
190 #define IC0_CFG2RD 0xB0400050
191 #define IC0_CFG2SET 0xB0400050
192 #define IC0_CFG2CLR 0xB0400054
194 #define IC0_REQ0INT 0xB0400054
195 #define IC0_SRCRD 0xB0400058
196 #define IC0_SRCSET 0xB0400058
197 #define IC0_SRCCLR 0xB040005C
198 #define IC0_REQ1INT 0xB040005C
200 #define IC0_ASSIGNRD 0xB0400060
201 #define IC0_ASSIGNSET 0xB0400060
202 #define IC0_ASSIGNCLR 0xB0400064
204 #define IC0_WAKERD 0xB0400068
205 #define IC0_WAKESET 0xB0400068
206 #define IC0_WAKECLR 0xB040006C
208 #define IC0_MASKRD 0xB0400070
209 #define IC0_MASKSET 0xB0400070
210 #define IC0_MASKCLR 0xB0400074
212 #define IC0_RISINGRD 0xB0400078
213 #define IC0_RISINGCLR 0xB0400078
214 #define IC0_FALLINGRD 0xB040007C
215 #define IC0_FALLINGCLR 0xB040007C
217 #define IC0_TESTBIT 0xB0400080
220 #define IC1_CFG0RD 0xB1800040
221 #define IC1_CFG0SET 0xB1800040
222 #define IC1_CFG0CLR 0xB1800044
224 #define IC1_CFG1RD 0xB1800048
225 #define IC1_CFG1SET 0xB1800048
226 #define IC1_CFG1CLR 0xB180004C
228 #define IC1_CFG2RD 0xB1800050
229 #define IC1_CFG2SET 0xB1800050
230 #define IC1_CFG2CLR 0xB1800054
232 #define IC1_REQ0INT 0xB1800054
233 #define IC1_SRCRD 0xB1800058
234 #define IC1_SRCSET 0xB1800058
235 #define IC1_SRCCLR 0xB180005C
236 #define IC1_REQ1INT 0xB180005C
238 #define IC1_ASSIGNRD 0xB1800060
239 #define IC1_ASSIGNSET 0xB1800060
240 #define IC1_ASSIGNCLR 0xB1800064
242 #define IC1_WAKERD 0xB1800068
243 #define IC1_WAKESET 0xB1800068
244 #define IC1_WAKECLR 0xB180006C
246 #define IC1_MASKRD 0xB1800070
247 #define IC1_MASKSET 0xB1800070
248 #define IC1_MASKCLR 0xB1800074
250 #define IC1_RISINGRD 0xB1800078
251 #define IC1_RISINGCLR 0xB1800078
252 #define IC1_FALLINGRD 0xB180007C
253 #define IC1_FALLINGCLR 0xB180007C
255 #define IC1_TESTBIT 0xB1800080
258 #define INTC_INT_DISABLED 0
259 #define INTC_INT_RISE_EDGE 0x1
260 #define INTC_INT_FALL_EDGE 0x2
261 #define INTC_INT_RISE_AND_FALL_EDGE 0x3
262 #define INTC_INT_HIGH_LEVEL 0x5
263 #define INTC_INT_LOW_LEVEL 0x6
264 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
267 #define AU1X00_UART0_INT 0
363 /* Programmable Counters 0 and 1 */
364 #define SYS_BASE 0xB1900000
365 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
384 #define SYS_CNTRL_C0S (1<<0)
386 /* Programmable Counter 0 Registers */
387 #define SYS_TOYTRIM (SYS_BASE + 0)
390 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
391 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
392 #define SYS_TOYREAD (SYS_BASE + 0x40)
395 #define SYS_RTCTRIM (SYS_BASE + 0x44)
396 #define SYS_RTCWRITE (SYS_BASE + 0x48)
397 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
398 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
399 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
400 #define SYS_RTCREAD (SYS_BASE + 0x58)
403 #define I2S_DATA 0xB1000000
404 #define I2S_DATA_MASK (0xffffff)
405 #define I2S_CONFIG 0xB1000004
420 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
421 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
422 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
423 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
426 #define I2S_CONFIG_SZ_BIT 0
427 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
429 #define I2S_CONTROL 0xB1000008
431 #define I2S_CONTROL_CE (1<<0)
435 #define USB_OHCI_BASE 0x10100000
436 #define USB_OHCI_LEN 0x00100000
437 #define USB_HOST_CONFIG 0xB017fffc
440 #define USBD_EP0RD 0xB0200000
441 #define USBD_EP0WR 0xB0200004
442 #define USBD_EP2WR 0xB0200008
443 #define USBD_EP3WR 0xB020000C
444 #define USBD_EP4RD 0xB0200010
445 #define USBD_EP5RD 0xB0200014
446 #define USBD_INTEN 0xB0200018
447 #define USBD_INTSTAT 0xB020001C
450 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
451 #define USBDEV_INT_CMPLT_BIT 0
452 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
453 #define USBD_CONFIG 0xB0200020
454 #define USBD_EP0CS 0xB0200024
455 #define USBD_EP2CS 0xB0200028
456 #define USBD_EP3CS 0xB020002C
457 #define USBD_EP4CS 0xB0200030
458 #define USBD_EP5CS 0xB0200034
464 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
465 #define USBDEV_CS_STALL (1<<0)
466 #define USBD_EP0RDSTAT 0xB0200040
467 #define USBD_EP0WRSTAT 0xB0200044
468 #define USBD_EP2WRSTAT 0xB0200048
469 #define USBD_EP3WRSTAT 0xB020004C
470 #define USBD_EP4RDSTAT 0xB0200050
471 #define USBD_EP5RDSTAT 0xB0200054
475 #define USBDEV_FSTAT_FCNT_BIT 0
476 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
477 #define USBD_ENABLE 0xB0200058
479 #define USBDEV_CE (1<<0)
482 #define AU1000_ETH0_BASE 0xB0500000
483 #define AU1000_ETH1_BASE 0xB0510000
484 #define AU1500_ETH0_BASE 0xB1500000
485 #define AU1500_ETH1_BASE 0xB1510000
486 #define AU1100_ETH0_BASE 0xB0500000
487 #define AU1550_ETH0_BASE 0xB0500000
488 #define AU1550_ETH1_BASE 0xB0510000
491 #define MAC_CONTROL 0x0
495 #define MAC_SET_BL(X) (((X)&0x3)<<6)
507 #define MAC_NORMAL_MODE 0
513 #define MAC_ADDRESS_HIGH 0x4
514 #define MAC_ADDRESS_LOW 0x8
515 #define MAC_MCAST_HIGH 0xC
516 #define MAC_MCAST_LOW 0x10
517 #define MAC_MII_CNTRL 0x14
518 #define MAC_MII_BUSY (1<<0)
519 #define MAC_MII_READ 0
521 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
522 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
523 #define MAC_MII_DATA 0x18
524 #define MAC_FLOW_CNTRL 0x1C
525 #define MAC_FLOW_CNTRL_BUSY (1<<0)
528 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
529 #define MAC_VLAN1_TAG 0x20
530 #define MAC_VLAN2_TAG 0x24
533 #define AU1000_MAC0_ENABLE 0xB0520000
534 #define AU1000_MAC1_ENABLE 0xB0520004
535 #define AU1500_MAC0_ENABLE 0xB1520000
536 #define AU1500_MAC1_ENABLE 0xB1520004
537 #define AU1100_MAC0_ENABLE 0xB0520000
538 #define AU1550_MAC0_ENABLE 0xB0520000
539 #define AU1550_MAC1_ENABLE 0xB0520004
541 #define MAC_EN_CLOCK_ENABLE (1<<0)
543 #define MAC_EN_TOSS (0<<2)
551 #define MAC0_TX_DMA_ADDR 0xB4004000
552 #define MAC1_TX_DMA_ADDR 0xB4004200
554 #define MAC_TX_BUFF0_STATUS 0x0
555 #define TX_FRAME_ABORTED (1<<0)
565 #define TX_COLL_CNT_MASK (0xF<<10)
567 #define MAC_TX_BUFF0_ADDR 0x4
568 #define TX_DMA_ENABLE (1<<0)
570 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
571 #define MAC_TX_BUFF0_LEN 0x8
572 #define MAC_TX_BUFF1_STATUS 0x10
573 #define MAC_TX_BUFF1_ADDR 0x14
574 #define MAC_TX_BUFF1_LEN 0x18
575 #define MAC_TX_BUFF2_STATUS 0x20
576 #define MAC_TX_BUFF2_ADDR 0x24
577 #define MAC_TX_BUFF2_LEN 0x28
578 #define MAC_TX_BUFF3_STATUS 0x30
579 #define MAC_TX_BUFF3_ADDR 0x34
580 #define MAC_TX_BUFF3_LEN 0x38
582 #define MAC0_RX_DMA_ADDR 0xB4004100
583 #define MAC1_RX_DMA_ADDR 0xB4004300
585 #define MAC_RX_BUFF0_STATUS 0x0
586 #define RX_FRAME_LEN_MASK 0x3fff
609 #define MAC_RX_BUFF0_ADDR 0x4
610 #define RX_DMA_ENABLE (1<<0)
612 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
613 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
614 #define MAC_RX_BUFF1_STATUS 0x10
615 #define MAC_RX_BUFF1_ADDR 0x14
616 #define MAC_RX_BUFF2_STATUS 0x20
617 #define MAC_RX_BUFF2_ADDR 0x24
618 #define MAC_RX_BUFF3_STATUS 0x30
619 #define MAC_RX_BUFF3_ADDR 0x34
622 /* UARTS 0-3 */
623 #define UART0_ADDR 0xB1100000
624 #define UART1_ADDR 0xB1200000
625 #define UART2_ADDR 0xB1300000
626 #define UART3_ADDR 0xB1400000
630 #define UART_RX 0 /* Receive buffer */
633 #define UART_IIR 0xC /* Interrupt ID Register */
634 #define UART_FCR 0x10 /* FIFO Control Register */
635 #define UART_LCR 0x14 /* Line Control Register */
636 #define UART_MCR 0x18 /* Modem Control Register */
637 #define UART_LSR 0x1C /* Line Status Register */
638 #define UART_MSR 0x20 /* Modem Status Register */
639 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
640 #define UART_ENABLE 0x100 /* Uart enable */
645 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
646 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
647 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
648 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
649 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
650 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
651 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
652 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
653 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
654 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
655 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
656 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
657 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
662 #define UART_LCR_SBC 0x40 /* Set break control */
663 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
664 #define UART_LCR_EPAR 0x10 /* Even parity select */
665 #define UART_LCR_PARITY 0x08 /* Parity Enable */
666 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
667 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
668 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
669 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
670 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
675 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
676 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
677 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
678 #define UART_LSR_FE 0x08 /* Frame error indicator */
679 #define UART_LSR_PE 0x04 /* Parity error indicator */
680 #define UART_LSR_OE 0x02 /* Overrun error indicator */
681 #define UART_LSR_DR 0x01 /* Receiver data ready */
686 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
687 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
688 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
689 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
690 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
691 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
696 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
697 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
698 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
699 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
704 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
705 #define UART_MCR_OUT2 0x08 /* Out2 complement */
706 #define UART_MCR_OUT1 0x04 /* Out1 complement */
707 #define UART_MCR_RTS 0x02 /* RTS complement */
708 #define UART_MCR_DTR 0x01 /* DTR complement */
713 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
714 #define UART_MSR_RI 0x40 /* Ring Indicator */
715 #define UART_MSR_DSR 0x20 /* Data Set Ready */
716 #define UART_MSR_CTS 0x10 /* Clear to Send */
717 #define UART_MSR_DDCD 0x08 /* Delta DCD */
718 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
719 #define UART_MSR_DDSR 0x02 /* Delta DSR */
720 #define UART_MSR_DCTS 0x01 /* Delta CTS */
721 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
725 #define SSI0_STATUS 0xB1600000
730 #define SSI_STATUS_B (1<<0)
731 #define SSI0_INT 0xB1600004
735 #define SSI0_INT_ENABLE 0xB1600008
739 #define SSI0_CONFIG 0xB1600020
743 #define SSI_CONFIG_ALEN_MASK (0x7<<20)
745 #define SSI_CONFIG_DLEN_MASK (0x7<<16)
749 #define SSI_CONFIG_BM_MASK (0x3<<8)
754 #define SSI0_ADATA 0xB1600024
757 #define SSI_AD_ADDR_MASK (0xff<<16)
758 #define SSI_AD_DATA_BIT 0
759 #define SSI_AD_DATA_MASK (0xfff<<0)
760 #define SSI0_CLKDIV 0xB1600028
761 #define SSI0_CONTROL 0xB1600100
763 #define SSI_CONTROL_E (1<<0)
766 #define SSI1_STATUS 0xB1680000
767 #define SSI1_INT 0xB1680004
768 #define SSI1_INT_ENABLE 0xB1680008
769 #define SSI1_CONFIG 0xB1680020
770 #define SSI1_ADATA 0xB1680024
771 #define SSI1_CLKDIV 0xB1680028
772 #define SSI1_ENABLE 0xB1680100
781 #define SSI_STATUS_B (1<<0)
806 #define SSI_CONFIG_BM_HI (0<<8)
811 #define SSI_ADATA_ADDR (0xFF<<16)
812 #define SSI_ADATA_DATA (0x0FFF)
816 #define SSI_ENABLE_E (1<<0)
820 #define IRDA_BASE 0xB0300000
821 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
822 #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
823 #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
824 #define IR_RING_SIZE (IRDA_BASE+0x0C)
825 #define IR_RING_PROMPT (IRDA_BASE+0x10)
826 #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
827 #define IR_INT_CLEAR (IRDA_BASE+0x18)
828 #define IR_CONFIG_1 (IRDA_BASE+0x20)
829 #define IR_RX_INVERT_LED (1<<0)
845 #define IR_SIR_FLAGS (IRDA_BASE+0x24)
846 #define IR_ENABLE (IRDA_BASE+0x28)
849 #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
850 #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
851 #define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
852 #define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
853 #define IR_CONFIG_2 (IRDA_BASE+0x3C)
854 #define IR_MODE_INV (1<<0)
856 #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
859 #define SYS_PINFUNC 0xB190002C
875 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
876 #define SYS_TRIOUTRD 0xB1900100
877 #define SYS_TRIOUTCLR 0xB1900100
878 #define SYS_OUTPUTRD 0xB1900108
879 #define SYS_OUTPUTSET 0xB1900108
880 #define SYS_OUTPUTCLR 0xB190010C
881 #define SYS_PINSTATERD 0xB1900110
882 #define SYS_PININPUTEN 0xB1900110
885 #define GPIO2_BASE 0xB1700000
886 #define GPIO2_DIR (GPIO2_BASE + 0)
888 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
889 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
890 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
893 #define SYS_SCRATCH0 0xB1900018
894 #define SYS_SCRATCH1 0xB190001C
895 #define SYS_WAKEMSK 0xB1900034
896 #define SYS_ENDIAN 0xB1900038
897 #define SYS_POWERCTRL 0xB190003C
898 #define SYS_WAKESRC 0xB190005C
899 #define SYS_SLPPWR 0xB1900078
900 #define SYS_SLEEP 0xB190007C
903 #define SYS_FREQCTRL0 0xB1900020
905 #define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT)
909 #define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT)
913 #define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT)
915 #define SYS_FC_FS0 (1<<0)
916 #define SYS_FREQCTRL1 0xB1900024
918 #define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT)
922 #define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT)
926 #define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT)
928 #define SYS_FC_FS3 (1<<0)
929 #define SYS_CLKSRC 0xB1900028
931 #define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT)
935 #define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT)
939 #define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT)
943 #define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT)
947 #define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT)
951 #define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT)
953 #define SYS_CS_CIR (1<<0)
955 #define SYS_CS_MUX_AUX 0x1
956 #define SYS_CS_MUX_FQ0 0x2
957 #define SYS_CS_MUX_FQ1 0x3
958 #define SYS_CS_MUX_FQ2 0x4
959 #define SYS_CS_MUX_FQ3 0x5
960 #define SYS_CS_MUX_FQ4 0x6
961 #define SYS_CS_MUX_FQ5 0x7
962 #define SYS_CPUPLL 0xB1900060
963 #define SYS_AUXPLL 0xB1900064
966 #define AC97C_CONFIG 0xB0000000
968 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
970 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
973 #define AC97C_RESET (1<<0)
974 #define AC97C_STATUS 0xB0000004
986 #define AC97C_RF (1<<0)
987 #define AC97C_DATA 0xB0000008
988 #define AC97C_CMD 0xB000000C
991 #define AC97C_INDEX_MASK 0x7f
992 #define AC97C_CNTRL 0xB0000010
994 #define AC97C_CE (1<<0)
996 #define DB1000_BCSR_ADDR 0xAE000000
997 #define DB1550_BCSR_ADDR 0xAF000000
1007 #define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */
1008 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1012 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1013 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1014 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1015 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1016 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1017 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1018 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1019 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1020 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1021 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1022 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1024 #define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr */
1028 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
1034 #define Au1500_EXT_CFG 0x600000000
1035 #define Au1500_EXT_CFG_TYPE1 0x680000000
1036 #define Au1500_PCI_IO_START 0x500000000
1037 #define Au1500_PCI_IO_END 0x5000FFFFF
1038 #define Au1500_PCI_MEM_START 0x440000000
1039 #define Au1500_PCI_MEM_END 0x443FFFFFF
1041 #define PCI_IO_START (Au1500_PCI_IO_START + 0x300)
1045 #define PCI_FIRST_DEVFN (0<<3)
1052 #define PCI_IO_START 0
1053 #define PCI_IO_END 0
1054 #define PCI_MEM_START 0
1055 #define PCI_MEM_END 0
1056 #define PCI_FIRST_DEVFN 0
1057 #define PCI_LAST_DEVFN 0
1059 #define AU1X_SOCK0_IO 0xF00000000
1060 #define AU1X_SOCK0_PHYS_ATTR 0xF40000000
1061 #define AU1X_SOCK0_PHYS_MEM 0xF80000000
1068 #define AU1X_SOCK1_IO 0xF04000000
1069 #define AU1X_SOCK1_PHYS_ATTR 0xF44000000
1070 #define AU1X_SOCK1_PHYS_MEM 0xF84000000