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/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/ebc-dev/epdlut/
H A Dpvi_waveform_v8.S19 .loc 1 383 0
26 add x29, sp, 0
31 .loc 1 384 0
34 .loc 1 383 0
36 .loc 1 384 0
41 .loc 1 284 0
52 .loc 1 298 0
54 .loc 1 302 0
56 .loc 1 300 0
58 .loc 1 301 0
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Des7202.c46 static int es7202_adc_num = 0;
60 {0x00, 0x10}, {0x01, 0x00}, {0x02, 0x04}, {0x03, 0x00},
61 {0x04, 0x01}, {0x05, 0x18}, {0x06, 0x00}, {0x07, 0x30},
62 {0x08, 0x02}, {0x10, 0xff}, {0x11, 0x0c}, {0x12, 0x55},
63 {0x13, 0x55}, {0x14, 0x8c}, {0x15, 0x33}, {0x16, 0x33},
64 {0x17, 0x33}, {0x18, 0x44}, {0x19, 0x00}, {0x1a, 0x00},
65 {0x1b, 0x00}, {0x1c, 0xf8}, {0x1d, 0x18}, {0x1e, 0x18},
71 u8 read_cmd[3] = { 0 }; in es7202_read()
72 u8 cmd_len = 0; in es7202_read()
74 read_cmd[0] = reg; in es7202_read()
[all …]
/OK3568_Linux_fs/kernel/lib/raid6/
H A Dneon.uc43 * The MASK() operation returns 0xFF in any byte for which the high
44 * bit is 1, 0x00 for any byte for which the high bit is 0.
63 const unative_t x1d = vdupq_n_u8(0x1d);
69 for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
71 for ( z = z0-1 ; z >= 0 ; z-- ) {
77 w2$$ = vandq_u8(w2$$, x1d);
94 const unative_t x1d = vdupq_n_u8(0x1d);
100 for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
111 w2$$ = vandq_u8(w2$$, x1d);
120 w2$$ = PMUL(w2$$, x1d);
[all …]
/OK3568_Linux_fs/kernel/crypto/
H A Dtestmgr.h33 * @ksize: Length of @key in bytes (0 if no key)
101 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
199 "\xDF\x8E\x8A\xE5\x9D\x73\x3D\x9F\x33\xB3\x01\x62\x4A\xFD\x1D\x51"
209 "\x5e\x32\x39\x6d\xc1\x1d\x7d\x50\x3b\x9f\x7a\xad\xf0\x2e\x25\x53"
216 "\x30\x82\x01\x1D" /* sequence of 285 bytes */
226 "\x7F\xE2\x53\x72\x98\xCA\x2A\x8F\x59\x46\xF8\xE5\xFD\x09\x1D\xBD"
265 "\xC6\x67\xFF\x1D\x1E\x3C\x1D\xC1\xB5\x5F\x6C\xC0\xB2\x07\x3A\x6D"
292 "\xA6\xFF\x46\x83\x97\xDE\xE9\xE2\x17\x03\x06\x14\xE2\xD7\xB1\x1D"
296 "\xA7\x1D\xD9\x1E\x06\xCD\xE8\xBA\x2C\x8C\x69\x32\xEA\xBE\x60\x71"
329 "\xC6\x67\xFF\x1D\x1E\x3C\x1D\xC1\xB5\x5F\x6C\xC0\xB2\x07\x3A\x6D"
[all …]
/OK3568_Linux_fs/kernel/drivers/media/usb/gspca/
H A Dov534.c29 #define OV534_REG_ADDRESS 0xf1 /* sensor address */
30 #define OV534_REG_SUBADDR 0xf2
31 #define OV534_REG_WRITE 0xf3
32 #define OV534_REG_READ 0xf4
33 #define OV534_REG_OPERATION 0xf5
34 #define OV534_REG_STATUS 0xf6
36 #define OV534_OP_WRITE_3 0x37
37 #define OV534_OP_WRITE_2 0x33
38 #define OV534_OP_READ_2 0xf9
96 .priv = 0},
[all …]
H A Dov534_9.c20 #define OV534_REG_ADDRESS 0xf1 /* sensor address */
21 #define OV534_REG_SUBADDR 0xf2
22 #define OV534_REG_WRITE 0xf3
23 #define OV534_REG_READ 0xf4
24 #define OV534_REG_OPERATION 0xf5
25 #define OV534_REG_STATUS 0xf6
27 #define OV534_OP_WRITE_3 0x37
28 #define OV534_OP_WRITE_2 0x33
29 #define OV534_OP_READ_2 0xf9
54 #define QVGA_MODE 0
[all …]
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dstv0900_init.h24 { 0, 11101 }, /*C/N=-0dB*/
83 { -5, 0xCAA1 }, /*-5dBm*/
84 { -10, 0xC229 }, /*-10dBm*/
85 { -15, 0xBB08 }, /*-15dBm*/
86 { -20, 0xB4BC }, /*-20dBm*/
87 { -25, 0xAD5A }, /*-25dBm*/
88 { -30, 0xA298 }, /*-30dBm*/
89 { -35, 0x98A8 }, /*-35dBm*/
90 { -40, 0x8389 }, /*-40dBm*/
91 { -45, 0x59BE }, /*-45dBm*/
[all …]
H A Ditd1000.c31 } while (0)
35 } while (0)
39 } while (0)
46 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1 in itd1000_write_regs()
56 buf[0] = reg; in itd1000_write_regs()
59 /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */ in itd1000_write_regs()
65 return 0; in itd1000_write_regs()
72 { .addr = state->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 }, in itd1000_read_reg()
77 itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1); in itd1000_read_reg()
100 { 0, 0x8, 0x3 },
[all …]
/OK3568_Linux_fs/kernel/include/dt-bindings/memory/
H A Drv1126-dram.h11 #define PHY_DDR3_RON_DISABLE (0x0)
12 #define PHY_DDR3_RON_455ohm (0x1)
13 #define PHY_DDR3_RON_230ohm (0x2)
14 #define PHY_DDR3_RON_153ohm (0x3)
15 #define PHY_DDR3_RON_115ohm (0x4)
16 #define PHY_DDR3_RON_91ohm (0x5)
17 #define PHY_DDR3_RON_76ohm (0x6)
18 #define PHY_DDR3_RON_65ohm (0x7)
19 #define PHY_DDR3_RON_57ohm (0x10)
20 #define PHY_DDR3_RON_51ohm (0x11)
[all …]
H A Drk3568-dram.h11 #define PHY_DDR4_DS_ODT_DISABLE (0x0)
12 #define PHY_DDR4_DS_ODT_556ohm (0x1)
13 #define PHY_DDR4_DS_ODT_279ohm (0x2)
14 #define PHY_DDR4_DS_ODT_185ohm (0x3)
15 #define PHY_DDR4_DS_ODT_139ohm (0x4)
16 #define PHY_DDR4_DS_ODT_111ohm (0x5)
17 #define PHY_DDR4_DS_ODT_93ohm (0x6)
18 #define PHY_DDR4_DS_ODT_79ohm (0x7)
19 #define PHY_DDR4_DS_ODT_69ohm (0x8)
20 #define PHY_DDR4_DS_ODT_62ohm (0x9)
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Datheros.c11 #define AR803x_PHY_DEBUG_ADDR_REG 0x1d
12 #define AR803x_PHY_DEBUG_DATA_REG 0x1e
14 #define AR803x_DEBUG_REG_5 0x5
15 #define AR803x_RGMII_TX_CLK_DLY 0x100
17 #define AR803x_DEBUG_REG_0 0x0
18 #define AR803x_RGMII_RX_CLK_DLY 0x8000
22 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
26 return 0; in ar8021_config()
52 return 0; in ar8031_config()
[all …]
/OK3568_Linux_fs/kernel/drivers/input/touchscreen/vtl_ts/
H A Dtp_fw.h3 0x02, 0x48, 0xA5, 0x02, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x4D, 0xE5, 0x00, 0x00,
4 0x00, 0x00, 0x00, 0x02, 0x3D, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x3D, 0xFF, 0x00, 0x00,
5 0x00, 0x00, 0x00, 0x02, 0x4C, 0xF6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x3D, 0xE5, 0x00, 0x00,
6 0x00, 0x00, 0x00, 0x02, 0x4E, 0x1D, 0x75, 0x86, 0x09, 0x75, 0x84, 0x9C, 0xD2, 0xA9, 0x22, 0x32,
7 0x90, 0x3F, 0xF0, 0x74, 0x56, 0xF0, 0xA3, 0x74, 0x54, 0xF0, 0xA3, 0x74, 0x4C, 0xF0, 0x22, 0x78,
8 0x95, 0x7C, 0x13, 0x7A, 0x4D, 0x79, 0x9D, 0x7F, 0x05, 0x12, 0x25, 0x27, 0x90, 0x13, 0xA3, 0x12,
9 0x41, 0x6A, 0xFF, 0xFF, 0xFF, 0xFF, 0x90, 0x13, 0xA7, 0x12, 0x41, 0x6A, 0x00, 0x00, 0x00, 0x00,
10 0x78, 0xBB, 0x7C, 0x13, 0x7A, 0x4D, 0x79, 0xA2, 0x7F, 0x0A, 0x12, 0x25, 0x27, 0x78, 0xC5, 0x7C,
11 0x13, 0x7D, 0x01, 0x7B, 0xFF, 0x7A, 0x4D, 0x79, 0xAC, 0x7E, 0x00, 0x7F, 0x14, 0x12, 0x40, 0x00,
12 0xC2, 0x1D, 0xE4, 0x90, 0x12, 0x38, 0xF0, 0x90, 0x12, 0x6E, 0xF0, 0x90, 0x12, 0x6F, 0xF0, 0x90,
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dt2081qds.dts104 #size-cells = <0>;
105 reg = <0x54 1>;
106 mux-mask = <0xe0>;
108 t2081mdio0: mdio@0 {
110 #size-cells = <0>;
111 reg = <0>;
114 reg = <0x1>;
120 #size-cells = <0>;
121 reg = <0x20>;
124 reg = <0x2>;
[all …]
/OK3568_Linux_fs/external/mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_com.c32 0, 0, 1, 0,
33 1, 2, 0, 1,
39 0, 1, 0, 2,
40 1, 0, 3, 2,
41 1, 0, 3, 2,
46 0, 0, 1, 0,
47 1, 2, 0, 1,
48 2, 3, 0, 1,
49 2, 3, 4, 0,
51 5, 0, 1, 2,
[all …]
/OK3568_Linux_fs/kernel/drivers/infiniband/hw/qib/
H A Dqib_6120_regs.h35 #define QIB_6120_Revision_OFFS 0x0
36 #define QIB_6120_Revision_R_Simulator_LSB 0x3F
37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
38 #define QIB_6120_Revision_Reserved_LSB 0x28
39 #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF
40 #define QIB_6120_Revision_BoardID_LSB 0x20
41 #define QIB_6120_Revision_BoardID_RMASK 0xFF
42 #define QIB_6120_Revision_R_SW_LSB 0x18
43 #define QIB_6120_Revision_R_SW_RMASK 0xFF
44 #define QIB_6120_Revision_R_Arch_LSB 0x10
[all …]
H A Dqib_7322_regs.h35 #define QIB_7322_Revision_OFFS 0x0
36 #define QIB_7322_Revision_DEF 0x0000000002010601
37 #define QIB_7322_Revision_R_Simulator_LSB 0x3F
38 #define QIB_7322_Revision_R_Simulator_MSB 0x3F
39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7322_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7322_Revision_R_Emulation_MSB 0x3E
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
43 #define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28
44 #define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i810/
H A Di810_drv.h60 #define DRIVER_PATCHLEVEL 0
139 #define I810_WRITE(reg, val) do { I810_DEREF(reg) = val; } while (0)
142 #define I810_WRITE16(reg, val) do { I810_DEREF16(reg) = val; } while (0)
144 #define I810_VERBOSE 0
157 } while (0)
164 } while (0)
172 } while (0)
174 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
175 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
177 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_2_1_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/OK3568_Linux_fs/u-boot/drivers/misc/
H A Drv1126-secure-otp.S9 .eabi_attribute 34, 0
25 .loc 1 172 0
27 @ args = 0, pretend = 0, frame = 0
28 @ frame_needed = 0, uses_anonymous_args = 0
31 .loc 1 175 0
37 .loc 1 165 0
42 .loc 1 178 0
43 moveq r0, #0
47 .loc 1 165 0
52 .loc 1 173 0
[all …]
/OK3568_Linux_fs/buildroot/dl/sox/git/src/
H A Dg711.c56 const uint8_t lsx_13linear2alaw[0x2000] = {
57 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
58 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
59 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
60 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
61 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
62 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
63 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
64 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
65 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/sis/
H A Doem300.h55 {0x08,0x08,0x08,0x08},
56 {0x08,0x08,0x08,0x08},
57 {0x08,0x08,0x08,0x08},
58 {0x2c,0x2c,0x2c,0x2c},
59 {0x08,0x08,0x08,0x08},
60 {0x08,0x08,0x08,0x08},
61 {0x08,0x08,0x08,0x08},
62 {0x20,0x20,0x20,0x20}
67 {0x20,0x20,0x20,0x20},
68 {0x20,0x20,0x20,0x20},
[all …]
/OK3568_Linux_fs/external/security/rk_tee_user/v2/export-ta_arm32/include/mbedtls/
H A Ddhm.h78 #define MBEDTLS_ERR_DHM_BAD_INPUT_DATA -0x3080 /**< Bad input parameters. */
79 #define MBEDTLS_ERR_DHM_READ_PARAMS_FAILED -0x3100 /**< Reading of the DHM paramete…
80 #define MBEDTLS_ERR_DHM_MAKE_PARAMS_FAILED -0x3180 /**< Making of the DHM parameter…
81 #define MBEDTLS_ERR_DHM_READ_PUBLIC_FAILED -0x3200 /**< Reading of the public value…
82 #define MBEDTLS_ERR_DHM_MAKE_PUBLIC_FAILED -0x3280 /**< Making of the public value …
83 #define MBEDTLS_ERR_DHM_CALC_SECRET_FAILED -0x3300 /**< Calculation of the DHM secr…
84 #define MBEDTLS_ERR_DHM_INVALID_FORMAT -0x3380 /**< The ASN.1 data is not forma…
85 #define MBEDTLS_ERR_DHM_ALLOC_FAILED -0x3400 /**< Allocation of memory failed…
86 #define MBEDTLS_ERR_DHM_FILE_IO_ERROR -0x3480 /**< Read or write of file faile…
89 #define MBEDTLS_ERR_DHM_HW_ACCEL_FAILED -0x3500 /**< DHM hardware accelerator fa…
[all …]

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