1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3568_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_DRAM_ROCKCHIP_RK3568_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/memory/rockchip-dram.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_DISABLE (0x0) 12*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_556ohm (0x1) 13*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_279ohm (0x2) 14*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_185ohm (0x3) 15*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_139ohm (0x4) 16*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_111ohm (0x5) 17*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_93ohm (0x6) 18*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_79ohm (0x7) 19*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_69ohm (0x8) 20*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_62ohm (0x9) 21*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_55ohm (0xa) 22*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_50ohm (0xb) 23*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_46ohm (0xc) 24*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_42ohm (0xd) 25*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_39ohm (0xe) 26*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_37ohm (0xf) 27*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_34ohm (0x18) 28*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_32ohm (0x19) 29*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_31ohm (0x1a) 30*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_29ohm (0x1b) 31*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_27ohm (0x1c) 32*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_26ohm (0x1d) 33*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_25ohm (0x1e) 34*4882a593Smuzhiyun #define PHY_DDR4_DS_ODT_24ohm (0x1f) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_DISABLE (0x0) 37*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_576ohm (0x1) 38*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_289ohm (0x2) 39*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_192ohm (0x3) 40*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_144ohm (0x4) 41*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_115ohm (0x5) 42*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_96ohm (0x6) 43*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_82ohm (0x7) 44*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_72ohm (0x8) 45*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_64ohm (0x9) 46*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_57ohm (0xa) 47*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_52ohm (0xb) 48*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_48ohm (0xc) 49*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_44ohm (0xd) 50*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_41ohm (0xe) 51*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_38ohm (0xf) 52*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_36ohm (0x18) 53*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_34ohm (0x19) 54*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_32ohm (0x1a) 55*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_30ohm (0x1b) 56*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_28ohm (0x1c) 57*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_27ohm (0x1d) 58*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_26ohm (0x1e) 59*4882a593Smuzhiyun #define PHY_LPDDR4_DS_ODT_25ohm (0x1f) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_DISABLE (0x0) 62*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_646ohm (0x1) 63*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_323ohm (0x2) 64*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_215ohm (0x3) 65*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_162ohm (0x4) 66*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_129ohm (0x5) 67*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_108ohm (0x6) 68*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_92ohm (0x7) 69*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_81ohm (0x8) 70*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_72ohm (0x9) 71*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_65ohm (0xa) 72*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_59ohm (0xb) 73*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_54ohm (0xc) 74*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_50ohm (0xd) 75*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_46ohm (0xe) 76*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_43ohm (0xf) 77*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_40ohm (0x18) 78*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_38ohm (0x19) 79*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_36ohm (0x1a) 80*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_34ohm (0x1b) 81*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_32ohm (0x1c) 82*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_31ohm (0x1d) 83*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_29ohm (0x1e) 84*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_UP_28ohm (0x1f) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_DISABLE (0x0) 87*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_513ohm (0x1) 88*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_259ohm (0x2) 89*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_172ohm (0x3) 90*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_130ohm (0x4) 91*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_104hm (0x5) 92*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_86hm (0x6) 93*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_74ohm (0x7) 94*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_65ohm (0x8) 95*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_58ohm (0x9) 96*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_52ohm (0xa) 97*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_47ohm (0xb) 98*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_43ohm (0xc) 99*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_40ohm (0xd) 100*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_37ohm (0xe) 101*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_35ohm (0xf) 102*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_32ohm (0x18) 103*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_30ohm (0x19) 104*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_29ohm (0x1a) 105*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_27ohm (0x1b) 106*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_26ohm (0x1c) 107*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_25ohm (0x1d) 108*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_24ohm (0x1e) 109*4882a593Smuzhiyun #define PHY_LPDDR4X_DS_ODT_DOWN_23ohm (0x1f) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK3568_H */ 112