Searched defs:pll_regs (Results 1 – 8 of 8) sorted by relevance
115 struct pll_regs { struct116 u32 cscr; /* Clock Source Control Register */117 u32 mpctl0; /* MCU PLL Control Register 0 */118 u32 mpctl1; /* MCU PLL Control Register 1 */119 u32 spctl0; /* System PLL Control Register 0 */120 u32 spctl1; /* System PLL Control Register 1 */121 u32 osc26mctl; /* Oscillator 26M Register */122 u32 pcdr0; /* Peripheral Clock Divider Register 0 */123 u32 pcdr1; /* Peripheral Clock Divider Register 1 */124 u32 pccr0; /* Peripheral Clock Control Register 0 */[all …]
1160 static const u32 pll_regs[] = { variable
108 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init() local
45 uint8_t pll_regs[6]; member
1257 uint8_t pll_regs[5]; in adau1373_set_pll() local
141 const struct cpu_dfs_regs *pll_regs; member
936 struct sensor_register pll_regs[] = { in ov2659_set_pixel_clock() local
3067 u8 pll_regs[16]; in atyfb_setup_sparc() local