Searched defs:VAL (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/drivers/nxp/clk/s32cc/include/ |
| H A D | s32cc-clk-regs.h | 29 #define FXOSC_CTRL_EOCV(VAL) (FXOSC_CTRL_EOCV_MASK & \ argument
33 #define FXOSC_CTRL_GM_SEL(VAL) (FXOSC_CTRL_GM_SEL_MASK & \ argument
50 #define PLLDIG_PLLDV_RDIV_SET(VAL) (PLLDIG_PLLDV_RDIV_MASK & \ argument
52 #define PLLDIG_PLLDV_RDIV(VAL) (((VAL) & PLLDIG_PLLDV_RDIV_MASK) >> \ argument
60 #define PLLDIG_PLLFD_MFN_SET(VAL) (PLLDIG_PLLFD_MFN_MASK & (VAL)) argument
68 #define PLLDIG_PLLODIV_DIV(VAL) (((VAL) & PLLDIG_PLLODIV_DIV_MASK) >> \ argument
70 #define PLLDIG_PLLODIV_DIV_SET(VAL) (PLLDIG_PLLODIV_DIV_MASK & ((VAL) << \ argument
101 #define MC_CGM_MUXn_DCm_DIV_SET(VAL) (MC_CGM_MUXn_DCm_DIV_MASK & ((VAL) \ argument
103 #define MC_CGM_MUXn_DCm_DIV(VAL) ((MC_CGM_MUXn_DCm_DIV_MASK & (VAL)) \ argument
122 #define DFS_PORTRESET_SET(VAL) (((VAL) & DFS_PORTRESET_MASK)) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/ |
| H A D | apupwr_clkctl_def.h | 71 #define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
72 #define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL) argument
74 #define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL) argument
75 #define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/apusys/ |
| H A D | mtk_apusys_apc_def.h | 85 #define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/devapc/ |
| H A D | devapc.h | 173 #define devapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
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