1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2026, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include "def.h" 14 #include <plat_common.h> 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #ifndef PLATFORM_STACK_SIZE 22 #define PLATFORM_STACK_SIZE U(0x440) 23 #endif 24 25 #define PLATFORM_CLUSTER_COUNT U(4) 26 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(2) /* 2 CPUs per cluster */ 27 28 /* Power domain descriptor prefix: entry for root + entry for total cluster count */ 29 #define PLAT_PWR_DOMAIN_PREFIX_SIZE U(2) 30 31 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) 32 33 #define E_INVALID_CORE_COUNT -1 34 #define E_INVALID_CLUSTER_COUNT -3 35 36 #define PLAT_MAX_PWR_LVL U(2) 37 #define PLAT_MAX_RET_STATE U(1) 38 #define PLAT_MAX_OFF_STATE U(2) 39 40 /******************************************************************************* 41 * BL31 specific defines. 42 ******************************************************************************/ 43 /* 44 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 45 * present). BL31_BASE is calculated using the current BL31 debug size plus a 46 * little space for growth. 47 */ 48 #ifndef MEM_BASE 49 # define BL31_BASE U(0xBBF00000) 50 # define BL31_LIMIT U(0xBC000000) 51 #else 52 # define BL31_BASE U(MEM_BASE) 53 # define BL31_LIMIT U(MEM_BASE + MEM_SIZE) 54 # ifdef MEM_PROGBITS_SIZE 55 # define BL31_PROGBITS_LIMIT U(MEM_BASE + \ 56 MEM_PROGBITS_SIZE) 57 # endif 58 #endif 59 60 /******************************************************************************* 61 * BL32 specific defines. 62 ******************************************************************************/ 63 #ifndef BL32_MEM_BASE 64 # define BL32_BASE U(0x01800000) 65 # define BL32_LIMIT U(0x09800000) 66 #else 67 # define BL32_BASE U(BL32_MEM_BASE) 68 # define BL32_LIMIT U(BL32_MEM_BASE + BL32_MEM_SIZE) 69 #endif 70 71 /******************************************************************************* 72 * BL33 specific defines. 73 ******************************************************************************/ 74 #ifndef PRELOADED_BL33_BASE 75 # define PLAT_ARM_NS_IMAGE_BASE U(0x40000000) 76 #else 77 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 78 #endif 79 80 /******************************************************************************* 81 * TSP specific defines. 82 ******************************************************************************/ 83 #define TSP_SEC_MEM_BASE BL32_BASE 84 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 85 86 /* ID of the secure physical generic timer interrupt used by the TSP */ 87 #define ARM_IRQ_SEC_PHY_TIMER U(29) 88 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 89 90 /******************************************************************************* 91 * Platform specific page table and MMU setup constants 92 ******************************************************************************/ 93 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 94 95 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) 96 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) 97 98 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 99 100 #define PLAT_OCM_BASE U(0xBBF00000) 101 #define PLAT_OCM_LIMIT U(0xBC000000) 102 103 #if TRANSFER_LIST 104 /* 105 * FIXME: This address should come from firmware before TF-A 106 * Having this to make sure the transfer list functionality works 107 */ 108 #define FW_HANDOFF_BASE U(0x1000000) 109 #define FW_HANDOFF_SIZE U(0x600000) 110 #endif 111 112 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 113 114 #ifndef MAX_MMAP_REGIONS 115 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 116 #define MAX_MMAP_REGIONS 11 117 #else 118 #define MAX_MMAP_REGIONS 10 119 #endif 120 #endif 121 122 #ifndef MAX_XLAT_TABLES 123 #define MAX_XLAT_TABLES U(12) 124 #endif 125 126 #define CACHE_WRITEBACK_SHIFT U(6) 127 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 128 129 #define PLAT_GICD_BASE_VALUE U(0xE2000000) 130 #define PLAT_GICR_BASE_VALUE U(0xE2060000) 131 #define PLAT_ARM_GICR_BASE PLAT_GICR_BASE_VALUE 132 #define PLAT_ARM_GICD_BASE PLAT_GICD_BASE_VALUE 133 134 /* 135 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 136 * terminology. On a GICv2 system or mode, the lists will be merged and treated 137 * as Group 0 interrupts. 138 */ 139 #define PLAT_IPI_IRQ 89 140 #define PLAT_VERSAL_IPI_IRQ PLAT_IPI_IRQ 141 142 #define PLAT_G1S_IRQ_PROPS(grp) \ 143 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 144 GIC_INTR_CFG_LEVEL) 145 146 #define PLAT_G0_IRQ_PROPS(grp) \ 147 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 148 GIC_INTR_CFG_EDGE), \ 149 INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \ 150 GIC_INTR_CFG_EDGE) 151 152 #define IRQ_MAX 220U 153 154 #endif /* PLATFORM_DEF_H */ 155