Merge branch 'master' of /home/wd/git/u-boot/custodians

sbc8548: allow enabling PCI via a make config option

Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CO

sbc8548: allow enabling PCI via a make config option

Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CONFIG_SYS_NS16550_CLK too, which was
not real user friendly,

This adds the typical PCI and clock speed make targets to the
toplevel Makefile in accordance with what is being done with
other boards (i.e. using the "-t" to mkconfig).

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: update PCI/PCI-e support code

The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile.

sbc8548: update PCI/PCI-e support code

The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile. This re-syncs it to match
the latest codebase and makes use of the new shared PCI functions
to reduce board duplication.

It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.

Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: correct local bus SDRAM size from 64M to 128M

The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was

sbc8548: correct local bus SDRAM size from 64M to 128M

The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: enable access to second bank of flash

The sbc8548 has a 64MB SODIMM flash module off of CS6 that
previously wasn't enumerated by u-boot. There were already
BR6/OR6 settings for it [used by

sbc8548: enable access to second bank of flash

The sbc8548 has a 64MB SODIMM flash module off of CS6 that
previously wasn't enumerated by u-boot. There were already
BR6/OR6 settings for it [used by cpu_init_f()] but there
was no TLB entry and it wasn't in the list of flash banks
reported to u-boot.

The location of the 64MB flash is "pulled back" 8MB from
a 64MB boundary, in order to allow address space for the
8MB boot flash that is at the end of 32 bit address space.
This means creating two 4MB TLB entries for the 8MB chunk,
and then expanding the original boot flash entry to 64MB
in order to cover the 8MB boot flash and the remainder
(56MB) of the user flash.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: delete unused MPC8548CDS info carried over from port

There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
t

sbc8548: delete unused MPC8548CDS info carried over from port

There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
the port to the sbc8548 board, so delete them.

Also, the form factor of the sbc8548 is a standalone board with a
single PCI-X and a single PCI-e slot. That pretty much guarantees
that it will never be a PCI agent itself, so the host/agent and root
complex/end node distinctions have been removed.

Similarly, since there is no physical connector mapping to PCI2, so
all references of PCI2 in the board support files have been removed
as well.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'next' of ../next

85xx: Remove unused CONFIG_CLEAR_LAW0 defines

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

85xx: Use common LSDMR defines from asm/fsl_lbc.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Merge git://git.denx.de/u-boot into u-boot

Merge branch 'master' into next

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

sbc8548: use proper PHY address

The values given for the PHY address were wrong, so the code
read no valid PHY ID, and fell through to the generic PHY
support, which would work on 1000M but would no

sbc8548: use proper PHY address

The values given for the PHY address were wrong, so the code
read no valid PHY ID, and fell through to the generic PHY
support, which would work on 1000M but would not auto negotiate
down to 100M or 10M.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

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sbc8548: enable command line editing by default.

Lets make things a bit more user friendly. It isn't 1985 anymore.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

sbc8548: don't enable the 3rd and 4th eTSEC

These interfaces don't have usable connectors on the board, so don't
bother enumerating or configuring them.

Signed-off-by: Paul Gortmaker <paul.gortmake

sbc8548: don't enable the 3rd and 4th eTSEC

These interfaces don't have usable connectors on the board, so don't
bother enumerating or configuring them.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

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Merge branch 'fixes' into cleanups

Conflicts:

board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/con

Merge branch 'fixes' into cleanups

Conflicts:

board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h

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Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master

Remove unused CONFIG_ADDR_STREAMING defines

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Removed unused CONFIG_L1_INIT_RAM symbol.

Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: An

Removed unused CONFIG_L1_INIT_RAM symbol.

Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

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Removed unused CONFIG_L1_INIT_RAM symbol.

Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.

Signed-off-by: Jon Loeliger <jdl@freescale.com>

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

85xx: Convert all fsl_pci_init users to new APIs

Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_p

85xx: Convert all fsl_pci_init users to new APIs

Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>

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Merge branch 'master' of /home/stefan/git/u-boot/u-boot

Merge git://git.denx.de/u-boot into x1

Conflicts:

drivers/usb/usb_ohci.c