1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * sbc8548 board configuration file 27 * 28 * Please refer to doc/README.sbc85xx for more info. 29 * 30 */ 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* High Level Configuration Options */ 35 #define CONFIG_BOOKE 1 /* BOOKE */ 36 #define CONFIG_E500 1 /* BOOKE e500 family */ 37 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 38 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 39 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 40 41 #undef CONFIG_PCI /* enable any pci type devices */ 42 #undef CONFIG_PCI1 /* PCI controller 1 */ 43 #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 44 #undef CONFIG_RIO 45 46 #ifdef CONFIG_PCI 47 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 48 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 49 #endif 50 #ifdef CONFIG_PCIE1 51 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 52 #endif 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 57 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 58 59 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 60 61 #define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ 62 63 /* 64 * These can be toggled for performance analysis, otherwise use default. 65 */ 66 #define CONFIG_L2_CACHE /* toggle L2 cache */ 67 #define CONFIG_BTB /* toggle branch predition */ 68 69 /* 70 * Only possible on E500 Version 2 or newer cores. 71 */ 72 #define CONFIG_ENABLE_36BIT_PHYS 1 73 74 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 75 76 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 78 #define CONFIG_SYS_MEMTEST_END 0x00400000 79 80 /* 81 * Base addresses -- Note these are effective addresses where the 82 * actual resources get mapped (not physical addresses) 83 */ 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 85 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 86 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 87 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 88 89 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 90 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 91 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 92 93 /* DDR Setup */ 94 #define CONFIG_FSL_DDR2 95 #undef CONFIG_FSL_DDR_INTERACTIVE 96 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 97 #undef CONFIG_DDR_SPD 98 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 99 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 101 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 102 103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 #define CONFIG_VERY_BIG_RAM 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 110 111 /* I2C addresses of SPD EEPROMs */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 113 114 /* 115 * Make sure required options are set 116 */ 117 #ifndef CONFIG_SPD_EEPROM 118 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 119 #endif 120 121 #undef CONFIG_CLOCKS_IN_MHZ 122 123 /* 124 * FLASH on the Local Bus 125 * Two banks, one 8MB the other 64MB, using the CFI driver. 126 * Boot from BR0/OR0 bank at 0xff80_0000 127 * Alternate BR6/OR6 bank at 0xfb80_0000 128 * 129 * BR0: 130 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 131 * Port Size = 8 bits = BRx[19:20] = 01 132 * Use GPCM = BRx[24:26] = 000 133 * Valid = BRx[31] = 1 134 * 135 * 0 4 8 12 16 20 24 28 136 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 137 * 138 * BR6: 139 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 140 * Port Size = 32 bits = BRx[19:20] = 11 141 * Use GPCM = BRx[24:26] = 000 142 * Valid = BRx[31] = 1 143 * 144 * 0 4 8 12 16 20 24 28 145 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 146 * 147 * OR0: 148 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 149 * XAM = OR0[17:18] = 11 150 * CSNT = OR0[20] = 1 151 * ACS = half cycle delay = OR0[21:22] = 11 152 * SCY = 6 = OR0[24:27] = 0110 153 * TRLX = use relaxed timing = OR0[29] = 1 154 * EAD = use external address latch delay = OR0[31] = 1 155 * 156 * 0 4 8 12 16 20 24 28 157 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 158 * 159 * OR6: 160 * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 161 * XAM = OR6[17:18] = 11 162 * CSNT = OR6[20] = 1 163 * ACS = half cycle delay = OR6[21:22] = 11 164 * SCY = 6 = OR6[24:27] = 0110 165 * TRLX = use relaxed timing = OR6[29] = 1 166 * EAD = use external address latch delay = OR6[31] = 1 167 * 168 * 0 4 8 12 16 20 24 28 169 * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6 170 */ 171 172 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 173 #define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ 174 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 175 176 #define CONFIG_SYS_BR0_PRELIM 0xff800801 177 #define CONFIG_SYS_BR6_PRELIM 0xfb801801 178 179 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 180 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 181 182 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 183 CONFIG_SYS_ALT_FLASH} 184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 185 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 186 #undef CONFIG_SYS_FLASH_CHECKSUM 187 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 188 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 189 190 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 191 192 #define CONFIG_FLASH_CFI_DRIVER 193 #define CONFIG_SYS_FLASH_CFI 194 #define CONFIG_SYS_FLASH_EMPTY_INFO 195 196 /* CS5 = Local bus peripherals controlled by the EPLD */ 197 198 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 199 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 200 #define CONFIG_SYS_EPLD_BASE 0xf8000000 201 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 202 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 203 #define CONFIG_SYS_BD_REV 0xf8300000 204 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 205 206 /* 207 * SDRAM on the Local Bus (CS3 and CS4) 208 */ 209 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 210 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 211 212 /* 213 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 214 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 215 * 216 * For BR3, need: 217 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 218 * port-size = 32-bits = BR2[19:20] = 11 219 * no parity checking = BR2[21:22] = 00 220 * SDRAM for MSEL = BR2[24:26] = 011 221 * Valid = BR[31] = 1 222 * 223 * 0 4 8 12 16 20 24 28 224 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 225 * 226 */ 227 228 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 229 230 /* 231 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 232 * 233 * For OR3, need: 234 * 64MB mask for AM, OR3[0:7] = 1111 1100 235 * XAM, OR3[17:18] = 11 236 * 10 columns OR3[19-21] = 011 237 * 12 rows OR3[23-25] = 011 238 * EAD set for extra time OR[31] = 0 239 * 240 * 0 4 8 12 16 20 24 28 241 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 242 */ 243 244 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 245 246 /* 247 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 248 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 249 * 250 * For BR4, need: 251 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 252 * port-size = 32-bits = BR2[19:20] = 11 253 * no parity checking = BR2[21:22] = 00 254 * SDRAM for MSEL = BR2[24:26] = 011 255 * Valid = BR[31] = 1 256 * 257 * 0 4 8 12 16 20 24 28 258 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 259 * 260 */ 261 262 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 263 264 /* 265 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 266 * 267 * For OR4, need: 268 * 64MB mask for AM, OR3[0:7] = 1111 1100 269 * XAM, OR3[17:18] = 11 270 * 10 columns OR3[19-21] = 011 271 * 12 rows OR3[23-25] = 011 272 * EAD set for extra time OR[31] = 0 273 * 274 * 0 4 8 12 16 20 24 28 275 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 276 */ 277 278 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 279 280 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 281 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 282 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 283 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 284 285 /* 286 * Common settings for all Local Bus SDRAM commands. 287 * At run time, either BSMA1516 (for CPU 1.1) 288 * or BSMA1617 (for CPU 1.0) (old) 289 * is OR'ed in too. 290 */ 291 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 292 | LSDMR_PRETOACT7 \ 293 | LSDMR_ACTTORW7 \ 294 | LSDMR_BL8 \ 295 | LSDMR_WRC4 \ 296 | LSDMR_CL3 \ 297 | LSDMR_RFEN \ 298 ) 299 300 #define CONFIG_SYS_INIT_RAM_LOCK 1 301 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 302 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 303 304 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 305 306 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 307 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 308 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 309 310 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 311 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 312 313 /* Serial Port */ 314 #define CONFIG_CONS_INDEX 1 315 #undef CONFIG_SERIAL_SOFTWARE_FIFO 316 #define CONFIG_SYS_NS16550 317 #define CONFIG_SYS_NS16550_SERIAL 318 #define CONFIG_SYS_NS16550_REG_SIZE 1 319 #define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */ 320 321 #define CONFIG_SYS_BAUDRATE_TABLE \ 322 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 323 324 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 325 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 326 327 /* Use the HUSH parser */ 328 #define CONFIG_SYS_HUSH_PARSER 329 #ifdef CONFIG_SYS_HUSH_PARSER 330 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 331 #endif 332 333 /* pass open firmware flat tree */ 334 #define CONFIG_OF_LIBFDT 1 335 #define CONFIG_OF_BOARD_SETUP 1 336 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 337 338 /* 339 * I2C 340 */ 341 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 342 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 343 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 344 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 345 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 346 #define CONFIG_SYS_I2C_SLAVE 0x7F 347 #define CONFIG_SYS_I2C_OFFSET 0x3000 348 349 /* 350 * General PCI 351 * Memory space is mapped 1-1, but I/O space must start from 0. 352 */ 353 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 354 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 355 356 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 357 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 358 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 359 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 360 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 361 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 362 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 363 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 364 365 #ifdef CONFIG_PCIE1 366 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 367 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 368 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 369 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 370 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 371 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 372 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 373 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 374 #endif 375 376 #ifdef CONFIG_RIO 377 /* 378 * RapidIO MMU 379 */ 380 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 381 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 382 #endif 383 384 #if defined(CONFIG_PCI) 385 386 #define CONFIG_NET_MULTI 387 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 388 389 #undef CONFIG_EEPRO100 390 #undef CONFIG_TULIP 391 392 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 393 394 #endif /* CONFIG_PCI */ 395 396 397 #if defined(CONFIG_TSEC_ENET) 398 399 #ifndef CONFIG_NET_MULTI 400 #define CONFIG_NET_MULTI 1 401 #endif 402 403 #define CONFIG_MII 1 /* MII PHY management */ 404 #define CONFIG_TSEC1 1 405 #define CONFIG_TSEC1_NAME "eTSEC0" 406 #define CONFIG_TSEC2 1 407 #define CONFIG_TSEC2_NAME "eTSEC1" 408 #undef CONFIG_MPC85XX_FEC 409 410 #define TSEC1_PHY_ADDR 0x19 411 #define TSEC2_PHY_ADDR 0x1a 412 413 #define TSEC1_PHYIDX 0 414 #define TSEC2_PHYIDX 0 415 416 #define TSEC1_FLAGS TSEC_GIGABIT 417 #define TSEC2_FLAGS TSEC_GIGABIT 418 419 /* Options are: eTSEC[0-3] */ 420 #define CONFIG_ETHPRIME "eTSEC0" 421 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 422 #endif /* CONFIG_TSEC_ENET */ 423 424 /* 425 * Environment 426 */ 427 #define CONFIG_ENV_IS_IN_FLASH 1 428 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 429 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 430 #define CONFIG_ENV_SIZE 0x2000 431 432 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 433 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 434 435 /* 436 * BOOTP options 437 */ 438 #define CONFIG_BOOTP_BOOTFILESIZE 439 #define CONFIG_BOOTP_BOOTPATH 440 #define CONFIG_BOOTP_GATEWAY 441 #define CONFIG_BOOTP_HOSTNAME 442 443 444 /* 445 * Command line configuration. 446 */ 447 #include <config_cmd_default.h> 448 449 #define CONFIG_CMD_PING 450 #define CONFIG_CMD_I2C 451 #define CONFIG_CMD_MII 452 #define CONFIG_CMD_ELF 453 454 #if defined(CONFIG_PCI) 455 #define CONFIG_CMD_PCI 456 #endif 457 458 459 #undef CONFIG_WATCHDOG /* watchdog disabled */ 460 461 /* 462 * Miscellaneous configurable options 463 */ 464 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 465 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 466 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 467 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 468 #if defined(CONFIG_CMD_KGDB) 469 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 470 #else 471 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 472 #endif 473 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 474 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 475 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 476 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 477 478 /* 479 * For booting Linux, the board info and command line data 480 * have to be in the first 8 MB of memory, since this is 481 * the maximum mapped by the Linux kernel during initialization. 482 */ 483 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 484 485 /* 486 * Internal Definitions 487 * 488 * Boot Flags 489 */ 490 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 491 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 492 493 #if defined(CONFIG_CMD_KGDB) 494 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 495 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 496 #endif 497 498 /* 499 * Environment Configuration 500 */ 501 502 /* The mac addresses for all ethernet interface */ 503 #if defined(CONFIG_TSEC_ENET) 504 #define CONFIG_HAS_ETH0 505 #define CONFIG_ETHADDR 02:E0:0C:00:00:FD 506 #define CONFIG_HAS_ETH1 507 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 508 #endif 509 510 #define CONFIG_IPADDR 192.168.0.55 511 512 #define CONFIG_HOSTNAME sbc8548 513 #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx 514 #define CONFIG_BOOTFILE /uImage 515 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 516 517 #define CONFIG_SERVERIP 192.168.0.2 518 #define CONFIG_GATEWAYIP 192.168.0.1 519 #define CONFIG_NETMASK 255.255.255.0 520 521 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 522 523 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 524 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 525 526 #define CONFIG_BAUDRATE 115200 527 528 #define CONFIG_EXTRA_ENV_SETTINGS \ 529 "netdev=eth0\0" \ 530 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 531 "tftpflash=tftpboot $loadaddr $uboot; " \ 532 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 533 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 534 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 535 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 536 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 537 "consoledev=ttyS0\0" \ 538 "ramdiskaddr=2000000\0" \ 539 "ramdiskfile=uRamdisk\0" \ 540 "fdtaddr=c00000\0" \ 541 "fdtfile=sbc8548.dtb\0" 542 543 #define CONFIG_NFSBOOTCOMMAND \ 544 "setenv bootargs root=/dev/nfs rw " \ 545 "nfsroot=$serverip:$rootpath " \ 546 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 547 "console=$consoledev,$baudrate $othbootargs;" \ 548 "tftp $loadaddr $bootfile;" \ 549 "tftp $fdtaddr $fdtfile;" \ 550 "bootm $loadaddr - $fdtaddr" 551 552 553 #define CONFIG_RAMBOOTCOMMAND \ 554 "setenv bootargs root=/dev/ram rw " \ 555 "console=$consoledev,$baudrate $othbootargs;" \ 556 "tftp $ramdiskaddr $ramdiskfile;" \ 557 "tftp $loadaddr $bootfile;" \ 558 "tftp $fdtaddr $fdtfile;" \ 559 "bootm $loadaddr $ramdiskaddr $fdtaddr" 560 561 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 562 563 #endif /* __CONFIG_H */ 564