video/drm: rockchip_phy: Add support to change lvds output voltage

This patch add support to change LVDS output common mode voltage
and differential voltage using dts prop "inno,lvds-vcom" and
"inno

video/drm: rockchip_phy: Add support to change lvds output voltage

This patch add support to change LVDS output common mode voltage
and differential voltage using dts prop "inno,lvds-vcom" and
"inno,lvds-vod".

&video_phy0 {
inno,lvds-vcom = <950>; /* 950mV */
inno,lvds-vod = <350>; /* 350mV */
}

Change-Id: Ia1f652d19af73910d98ed8844ec3248bd2ac510a
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>

show more ...

video/drm: phy: dcphy: optimize signal

Type: Fix
Redmine ID: #487592
Associated modifications: N/A
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ic504f6a16c1a401698

video/drm: phy: dcphy: optimize signal

Type: Fix
Redmine ID: #487592
Associated modifications: N/A
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ic504f6a16c1a401698bc066cd7ee2cdbfc7fd9cf

show more ...

video/drm: rgb: add dclk_delayline config for rk3576

The dclk_delayline is to adjust the phase between dclk
and data for bt1120/bt656/rgb interface.

According to the rk3576 SI test report, the dclk

video/drm: rgb: add dclk_delayline config for rk3576

The dclk_delayline is to adjust the phase between dclk
and data for bt1120/bt656/rgb interface.

According to the rk3576 SI test report, the dclk_delayline
should be 0x5 in order to improve signal quality.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Id36b3dc1dee1965d8250be721c01aaf9788014b2

show more ...

video/drm: rgb: add mode_valid to validate display mode

Add struct rockchip_rgb_data with new parameters rgb_max_dclk_rate
and mcu_max_dclk_rate in order to limit resolution on
some platform, such a

video/drm: rgb: add mode_valid to validate display mode

Add struct rockchip_rgb_data with new parameters rgb_max_dclk_rate
and mcu_max_dclk_rate in order to limit resolution on
some platform, such as RV1106.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ic765acc044d9c347860ffe1288a9e7766a9fbf1b

show more ...

video/drm: vop2: add te config for mipi cmd mode in rk3562

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I669e7f97e40e290f307d3fba4c7a4eb354e80cf8

video/drm: analogix_dp: add support for rate R216/R243/R324/R432

R216/R243/R324/R432 are the new recommended link rates in
eDP v1.4, which may be read from DPCD SUPPORTED_LINK_RATES
(0x00010h throug

video/drm: analogix_dp: add support for rate R216/R243/R324/R432

R216/R243/R324/R432 are the new recommended link rates in
eDP v1.4, which may be read from DPCD SUPPORTED_LINK_RATES
(0x00010h through 0x0001fh). And set the link rate by DPCD
LINK_BW_SET(0x00100h).

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I68ed7020c87e9e4453128890e3ca42b875455b80

show more ...

video/drm: analogix_dp: add support to parse link rate for eDP v1.4

As Table 4-23 in eDP v1.4 spec, the link rate can be
read from SUPPORTED_LINK_RATES(0x00010h through 0x0001fh),
which is required

video/drm: analogix_dp: add support to parse link rate for eDP v1.4

As Table 4-23 in eDP v1.4 spec, the link rate can be
read from SUPPORTED_LINK_RATES(0x00010h through 0x0001fh),
which is required for sink devices.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: If747462b9c4b37ee643e9ca08e4daf397cbdce9d

show more ...

video/drm: dp_helper: fix conversion function of bw code and link rate

Synchronize the conversion function of bw code and link
rate with kernel, which can be compatible with more link
rates.

Signed

video/drm: dp_helper: fix conversion function of bw code and link rate

Synchronize the conversion function of bw code and link
rate with kernel, which can be compatible with more link
rates.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I7cb374738f6e8137a5221d53465ae0cd04f38c7e

show more ...

video/drm: vop2: disable aclk pre auto gating in global init process

This is a workaround for RK3528/RK3562/RK3576:

The aclk pre auto gating function may disable the aclk
in some unexpected cases,

video/drm: vop2: disable aclk pre auto gating in global init process

This is a workaround for RK3528/RK3562/RK3576:

The aclk pre auto gating function may disable the aclk
in some unexpected cases, which detected by hardware
automatically.

For example, if the above function is enabled, the post
scale function will be affected, resulting in abnormal
display.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ib0aa6828de57ea35140b42d6c9e21ee3512837b6

show more ...

video/drm: dsi2: enable hs clk once the init cmds be sent by default

the host processor to keep the HS serial clock running for the
peripheral which may not generate its own clock to complete
proces

video/drm: dsi2: enable hs clk once the init cmds be sent by default

the host processor to keep the HS serial clock running for the
peripheral which may not generate its own clock to complete
processing or pipeline movement of received data.

Change-Id: If4f6d5ed916740bd433d8c1dafd8a421e1ffa950
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

show more ...

edid: Don't send non-zero YQ in AVI infoframe for HDMI 1.x sinks

Apparently some sinks look at the YQ bits even when receiving RGB,
and they get somehow confused when they see a non-zero YQ value.
S

edid: Don't send non-zero YQ in AVI infoframe for HDMI 1.x sinks

Apparently some sinks look at the YQ bits even when receiving RGB,
and they get somehow confused when they see a non-zero YQ value.
So we can't just blindly follow CEA-861-F and set YQ to match the
RGB range.

Unfortunately there is no good way to tell whether the sink
designer claims to have read CEA-861-F. The CEA extension block
revision number has generally been stuck at 3 since forever,
and even a very recently manufactured sink might be based on
an old design so the manufacturing date doesn't seem like
something we can use. In lieu of better information let's
follow CEA-861-F only for HDMI 2.0 sinks, since HDMI 2.0 is
based on CEA-861-F. For HDMI 1.x sinks we'll always set YQ=0.

Change-Id: If477d06e6dbbf1ef0f84ef35abb075a37ff17be1
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>

show more ...

video/drm: vop: add log to show actual dclk rate assigned from pll

The log may be like:

VOP:0x27900000 set crtc_clock to 51200KHz, get 50000000Hz

Signed-off-by: Damon Ding <damon.ding@rock-chips.c

video/drm: vop: add log to show actual dclk rate assigned from pll

The log may be like:

VOP:0x27900000 set crtc_clock to 51200KHz, get 50000000Hz

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I2bfeca09fd856e026f71ac88429a4f2da060fa10

show more ...

video/drm: dw-hdmi-qp: Optimized hdmi ddc transfer process

1.Reading edid consecutively 16 bytes at a time to
reduce the time consumed.

2.Increase the number of retries on failure to ensure
success

video/drm: dw-hdmi-qp: Optimized hdmi ddc transfer process

1.Reading edid consecutively 16 bytes at a time to
reduce the time consumed.

2.Increase the number of retries on failure to ensure
successful transfer.

Change-Id: I918ed91c19101afb7b3ce72ecf5d45aa17a76382
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>

show more ...

video/drm: vop2: move hactive 4-pixel alignment check to .mode_fixup()

The check in .mode_fixup() can take effect on the scenes
displayed in the panel or monitor.

Fixes: cc781e0266d ("video/drm: di

video/drm: vop2: move hactive 4-pixel alignment check to .mode_fixup()

The check in .mode_fixup() can take effect on the scenes
displayed in the panel or monitor.

Fixes: cc781e0266d ("video/drm: display: fix hactive 4-pixel alignment if using panel")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I089d9522ce3bf349e89785964d00de8f5f9bd461

show more ...

video/drm: vop2: adjust hfp and hbp for YUV420 output

For RK3576 YUV420 output, hden signal introduce one cycle delay,
so we need to adjust hfp and hbp to compatible with this design.

Related kerne

video/drm: vop2: adjust hfp and hbp for YUV420 output

For RK3576 YUV420 output, hden signal introduce one cycle delay,
so we need to adjust hfp and hbp to compatible with this design.

Related kernel commit:
0c56703c07d6 ("drm/rockchip: logo: call .mode_fixup() before mode comparison")

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I0c68cab7f1d3986269da806785317ee79c833843

show more ...

video/drm: tve: add support for parsing vdac_out_current from otp

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I054482609ade89a20747041e1ce958a02fa0463e

video/drm: vop2: get gamma config from dts

sample:

/ {
dsp_lut0: dsp-lut0 {
gamma-lut = <...>;
};

dsp_lut1: dsp-lut1 {
gamma-lut = <...>;
};
};

&vp0 {
dsp-lut = <&dsp_lut0>;
};

&vp1 {

video/drm: vop2: get gamma config from dts

sample:

/ {
dsp_lut0: dsp-lut0 {
gamma-lut = <...>;
};

dsp_lut1: dsp-lut1 {
gamma-lut = <...>;
};
};

&vp0 {
dsp-lut = <&dsp_lut0>;
};

&vp1 {
dsp-lut = <&dsp_lut1>;
};

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I9efbeb4640129307081e6df723194c5d3df0edb4

show more ...

video/drm: dsi2: support disable hold mode in cmd mode

Type: Function
Redmine ID: N/A
Associated modifications: N/A
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ic

video/drm: dsi2: support disable hold mode in cmd mode

Type: Function
Redmine ID: N/A
Associated modifications: N/A
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ic6a3625dea08760e72adc4b61a4cdbb5e4585438

show more ...

video/drm: dsi: normalize for dual-channel

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I5fb6e5f1d9111523206df8042ed304e3155c290d

video/drm: dsi2: normalize for dual-channel

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I25e234bd086d051f4473dcb91c0cb428f061628b

video/drm: dw_dp: create a device for dp port

when DPTX support mst, it will mulit port in dts as follow:
dp {
dp0 {
...
};
dp1 {
...
};
...
};

The display route is described in the child

video/drm: dw_dp: create a device for dp port

when DPTX support mst, it will mulit port in dts as follow:
dp {
dp0 {
...
};
dp1 {
...
};
...
};

The display route is described in the child node and not
the top device node. It's better to create a device for
the child node(dp0 node) for the rochchip display drvier
to parse the display route correctly.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ibf02e172eac22de83d86dcb7757fd162198234a7

show more ...

video/drm: display: check the string pointer before use

if there are no compatible property define, the dev_read_string
function will return a NULL pointer. And the strcmp will not
check whether the

video/drm: display: check the string pointer before use

if there are no compatible property define, the dev_read_string
function will return a NULL pointer. And the strcmp will not
check whether the poniter is NULL or not. So it's better to
check the string pointer before use to avoid NULL pointer issue
happen.

strcmp
compatible = dev_read_string(conn->dev, "compatible");
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I19a376a7c68a482a76afad51e9ffb400611de2b0

show more ...

Revert "video/drm: display: find device for DP-MST device node"

This reverts commit 0a69cd686a1b8d67ebe07a8f7be860d0fcee11bf.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Id

Revert "video/drm: display: find device for DP-MST device node"

This reverts commit 0a69cd686a1b8d67ebe07a8f7be860d0fcee11bf.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Id83494e5b59f447024ae4c1f1a787cc345861d11

show more ...

video/drm: display: fix Condition of CDR fail

In DP spec 1.3, Condition of CR fail are outlined
in section 3.5.1.2.2.1, figure 3-20:

1. Maximum Voltage Swing reached
2. Same Voltage five times

The

video/drm: display: fix Condition of CDR fail

In DP spec 1.3, Condition of CR fail are outlined
in section 3.5.1.2.2.1, figure 3-20:

1. Maximum Voltage Swing reached
2. Same Voltage five times

The following conditions have been optimized:
1. Training of CDR still failed while maximum voltage swing has been
applied and configured
2.Removed the redundant judgment for the maximum pre-emphasis level
reached

Change-Id: I560cbe9da273bfc1e532d0d8029d793a23938bc5
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

show more ...

video/drm: dw-hdmi-qp: Fix force 4k120 output yuv420

Change-Id: If5b4c822150798716048763cceefd5a41315f02e
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>