1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip HDMI/DP Combo PHY with Samsung IP block 4 * 5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <generic-phy.h> 11 #include <reset.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <linux/bitfield.h> 16 #include <linux/iopoll.h> 17 #include <asm/arch/clock.h> 18 19 #define HDPTXPHY_GRF_CON0 0x0000 20 #define RO_REF_CLK_SEL GENMASK(11, 10) 21 #define LC_REF_CLK_SEL GENMASK(9, 8) 22 #define PLL_EN BIT(7) 23 #define BIAS_EN BIT(6) 24 #define BGR_EN BIT(5) 25 #define HDPTX_MODE_SEL BIT(0) 26 #define HDPTXPHY_GRF_STATUS0 0x0080 27 #define PLL_LOCK_DONE BIT(3) 28 #define PHY_CLK_RDY BIT(2) 29 #define PHY_RDY BIT(1) 30 #define SB_RDY BIT(0) 31 32 /* cmn_reg0008 */ 33 #define OVRD_LCPLL_EN BIT(7) 34 #define LCPLL_EN BIT(6) 35 36 /* cmn_reg003C */ 37 #define ANA_LCPLL_RESERVED7 BIT(7) 38 39 /* cmn_reg003D */ 40 #define OVRD_ROPLL_EN BIT(7) 41 #define ROPLL_EN BIT(6) 42 43 /* cmn_reg0046 */ 44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4) 45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0) 46 47 /* cmn_reg0047 */ 48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3) 49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0) 50 51 /* cmn_reg004E */ 52 #define ANA_ROPLL_PI_EN BIT(5) 53 54 /* cmn_reg0051 */ 55 #define ROPLL_PMS_MDIV GENMASK(7, 0) 56 57 /* cmn_reg0055 */ 58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0) 59 60 /* cmn_reg0059 */ 61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4) 62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0) 63 64 /* cmn_reg005A */ 65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4) 66 #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0) 67 68 /* cmn_reg005B */ 69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4) 70 #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0) 71 72 /* cmn_reg005D */ 73 #define OVRD_ROPLL_REF_CLK_SEL BIT(5) 74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3) 75 76 /* cmn_reg005E */ 77 #define ANA_ROPLL_SDM_EN BIT(6) 78 #define OVRD_ROPLL_SDM_RSTN BIT(5) 79 #define ROPLL_SDM_RSTN BIT(4) 80 #define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3) 81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2) 82 #define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1) 83 #define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0) 84 85 /* cmn_reg005F */ 86 #define OVRD_ROPLL_SDC_RSTN BIT(5) 87 #define ROPLL_SDC_RSTN BIT(4) 88 89 /* cmn_reg0060 */ 90 #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0) 91 92 /* cmn_reg0064 */ 93 #define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3) 94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2) 95 #define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1) 96 #define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0) 97 98 /* cmn_reg0065 */ 99 #define ROPLL_SDM_NUMERATOR GENMASK(7, 0) 100 101 /* cmn_reg0069 */ 102 #define ROPLL_SDC_N_RBR GENMASK(2, 0) 103 104 /* cmn_reg006A */ 105 #define ROPLL_SDC_N_HBR GENMASK(5, 3) 106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0) 107 108 /* cmn_reg006B */ 109 #define ROPLL_SDC_N_HBR3 GENMASK(3, 1) 110 111 /* cmn_reg006C */ 112 #define ROPLL_SDC_NUMERATOR GENMASK(5, 0) 113 114 /* cmn_reg0070 */ 115 #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0) 116 117 /* cmn_reg0074 */ 118 #define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3) 119 #define ROPLL_SDC_NDIV_RSTN BIT(2) 120 #define OVRD_ROPLL_SSC_EN BIT(1) 121 #define ROPLL_SSC_EN BIT(0) 122 123 /* cmn_reg0075 */ 124 #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0) 125 126 /* cmn_reg0076 */ 127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2) 128 129 /* cmn_reg0077 */ 130 #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3) 131 132 /* cmn_reg0081 */ 133 #define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3) 134 #define ANA_PLL_CD_HSCLK_WEST_EN BIT(1) 135 #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0) 136 137 /* cmn_reg0082 */ 138 #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0) 139 140 /* cmn_reg0083 */ 141 #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5) 142 143 /* cmn_reg0084 */ 144 #define PLL_LCRO_CLK_SEL BIT(5) 145 146 /* cmn_reg0085 */ 147 #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0) 148 149 /* cmn_reg0087 */ 150 #define ANA_PLL_TX_HS_CLK_EN BIT(2) 151 152 /* cmn_reg0095 */ 153 #define DP_TX_LINK_BW GENMASK(1, 0) 154 155 /* cmn_reg0097 */ 156 #define DIG_CLK_SEL BIT(1) 157 158 /* cmn_reg0099 */ 159 #define SSC_EN GENMASK(7, 6) 160 #define CMN_ROPLL_ALONE_MODE BIT(2) 161 162 /* cmn_reg009A */ 163 #define HS_SPEED_SEL BIT(0) 164 165 /* cmn_reg009B */ 166 #define LS_SPEED_SEL BIT(4) 167 168 /* sb_reg0102 */ 169 #define OVRD_SB_RXTERM_EN BIT(5) 170 #define SB_RXRERM_EN BIT(4) 171 #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0) 172 173 /* sb_reg0103 */ 174 #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3) 175 #define OVRD_SB_RX_RESCAL_DONE BIT(1) 176 #define SB_RX_RESCAL_DONE BIT(0) 177 178 /* sb_reg0104 */ 179 #define OVRD_SB_EN BIT(5) 180 #define SB_EN BIT(4) 181 #define OVRD_SB_AUX_EN BIT(1) 182 #define SB_AUX_EN BIT(0) 183 184 /* sb_reg0105 */ 185 #define ANA_SB_TX_HLVL_PROG GENMASK(2, 0) 186 187 /* sb_reg0106 */ 188 #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4) 189 190 /* sb_reg010D */ 191 #define ANA_SB_DMRX_LPBK_DATA BIT(4) 192 193 /* sb_reg010F */ 194 #define OVRD_SB_VREG_EN BIT(7) 195 #define SB_VREG_EN BIT(6) 196 #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0) 197 198 /* sb_reg0110 */ 199 #define ANA_SB_VREG_OUT_SEL BIT(1) 200 #define ANA_SB_VREG_REF_SEL BIT(0) 201 202 /* sb_reg0113 */ 203 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4) 204 #define SB_RX_RTERM_CTRL GENMASK(3, 0) 205 206 /* sb_reg0114 */ 207 #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3) 208 #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0) 209 210 /* sb_reg0115 */ 211 #define SB_READY_DELAY_TIME GENMASK(5, 3) 212 #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0) 213 214 /* sb_reg0116 */ 215 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4) 216 217 /* sb_reg0117 */ 218 #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0) 219 220 /* sb_reg0118 */ 221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0) 222 223 /* sb_reg011A */ 224 #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0) 225 226 /* sb_reg011B */ 227 #define SB_EARC_SIG_DET_BYPASS BIT(4) 228 #define SB_AFC_TOL GENMASK(3, 0) 229 230 /* sb_reg011C */ 231 #define SB_AFC_STB_NUM GENMASK(3, 0) 232 233 /* sb_reg011D */ 234 #define SB_TG_OSC_CNT_MIN GENMASK(7, 0) 235 236 /* sb_reg011E */ 237 #define SB_TG_OSC_CNT_MAX GENMASK(7, 0) 238 239 /* sb_reg011F */ 240 #define SB_PWM_AFC_CTRL GENMASK(7, 2) 241 #define SB_RCAL_RSTN BIT(1) 242 243 /* sb_reg0120 */ 244 #define SB_AUX_EN_IN BIT(7) 245 246 /* sb_reg0123 */ 247 #define OVRD_SB_READY BIT(5) 248 #define SB_READY BIT(4) 249 250 /* lntop_reg0200 */ 251 #define PROTOCOL_SEL BIT(2) 252 253 /* lntop_reg0206 */ 254 #define DATA_BUS_WIDTH GENMASK(2, 1) 255 #define BUS_WIDTH_SEL BIT(0) 256 257 /* lntop_reg0207 */ 258 #define LANE_EN GENMASK(3, 0) 259 260 /* lane_reg0301 */ 261 #define OVRD_LN_TX_DRV_EI_EN BIT(7) 262 #define LN_TX_DRV_EI_EN BIT(6) 263 264 /* lane_reg0303 */ 265 #define OVRD_LN_TX_DRV_LVL_CTRL BIT(5) 266 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0) 267 268 /* lane_reg0304 */ 269 #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4) 270 #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0) 271 272 /* lane_reg0305 */ 273 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6) 274 #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2) 275 276 /* lane_reg0306 */ 277 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5) 278 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2) 279 #define LN_ANA_TX_DRV_ACCDRV_EN BIT(0) 280 281 /* lane_reg0307 */ 282 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6) 283 #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3) 284 285 /* lane_reg030A */ 286 #define LN_ANA_TX_JEQ_EN BIT(4) 287 #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0) 288 289 /* lane_reg030B */ 290 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4) 291 #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0) 292 293 /* lane_reg030C */ 294 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4) 295 #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0) 296 297 /* lane_reg030D */ 298 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4) 299 #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0) 300 301 /* lane_reg030E */ 302 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4) 303 304 /* lane_reg0310 */ 305 #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0) 306 307 /* lane_reg0311 */ 308 #define LN_TX_SER_40BIT_EN_RBR BIT(3) 309 #define LN_TX_SER_40BIT_EN_HBR BIT(2) 310 #define LN_TX_SER_40BIT_EN_HBR2 BIT(1) 311 #define LN_TX_SER_40BIT_EN_HBR3 BIT(0) 312 313 /* lane_reg0316 */ 314 #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0) 315 316 /* lane_reg031B */ 317 #define LN_ANA_TX_RESERVED GENMASK(7, 0) 318 319 /* lane_reg031E */ 320 #define LN_POLARITY_INV BIT(2) 321 #define LN_LANE_MODE BIT(1) 322 323 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset)) 324 325 struct rockchip_hdptx_phy { 326 struct udevice *dev; 327 struct regmap *regmap; 328 struct regmap *grf; 329 330 struct reset_ctl apb_reset; 331 struct reset_ctl cmn_reset; 332 struct reset_ctl init_reset; 333 struct reset_ctl lane_reset; 334 u32 lane_polarity_invert[4]; 335 }; 336 337 enum { 338 DP_BW_RBR, 339 DP_BW_HBR, 340 DP_BW_HBR2, 341 DP_BW_HBR3, 342 }; 343 344 enum { 345 EDP_BW_2_16, 346 EDP_BW_2_43, 347 EDP_BW_3_24, 348 EDP_BW_4_32, 349 }; 350 351 struct tx_drv_ctrl { 352 u8 tx_drv_lvl_ctrl; 353 u8 tx_drv_post_lvl_ctrl; 354 u8 ana_tx_drv_idrv_idn_ctrl; 355 u8 ana_tx_drv_idrv_iup_ctrl; 356 u8 ana_tx_drv_accdrv_en; 357 u8 ana_tx_drv_accdrv_ctrl; 358 } __packed; 359 360 struct tx_pll_ctrl { 361 u8 mdiv; 362 u8 sdiv; 363 u8 sdm_denominator; 364 u8 sdm_numerator_sign; 365 u8 sdm_numerator; 366 u8 sdc_clock_div; 367 u8 sdc_numerator; 368 u8 sdc_denominator; 369 u8 ssc_deviation; 370 u8 ssc_freq; 371 } __packed; 372 373 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = { 374 /* voltage swing 0, pre-emphasis 0->3 */ 375 { 376 { 0x1, 0x0, 0x4, 0x6, 0x0, 0x4 }, 377 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4 }, 378 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4 }, 379 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 380 }, 381 382 /* voltage swing 1, pre-emphasis 0->2 */ 383 { 384 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4 }, 385 { 0xa, 0x5, 0x4, 0x6, 0x0, 0x4 }, 386 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 387 }, 388 389 /* voltage swing 2, pre-emphasis 0->1 */ 390 { 391 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4 }, 392 { 0xd, 0x5, 0x7, 0x7, 0x1, 0x7 }, 393 }, 394 395 /* voltage swing 3, pre-emphasis 0 */ 396 { 397 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, 398 } 399 }; 400 401 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = { 402 /* voltage swing 0, pre-emphasis 0->3 */ 403 { 404 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, 405 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, 406 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4 }, 407 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 408 }, 409 410 /* voltage swing 1, pre-emphasis 0->2 */ 411 { 412 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, 413 { 0xb, 0x6, 0x4, 0x6, 0x0, 0x4 }, 414 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 415 }, 416 417 /* voltage swing 2, pre-emphasis 0->1 */ 418 { 419 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, 420 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, 421 }, 422 423 /* voltage swing 3, pre-emphasis 0 */ 424 { 425 { 0xd, 0x1, 0x7, 0x7, 0x1, 0x4 }, 426 } 427 }; 428 429 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = { 430 /* voltage swing 0, pre-emphasis 0->3 */ 431 { 432 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, 433 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, 434 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4 }, 435 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 436 }, 437 438 /* voltage swing 1, pre-emphasis 0->2 */ 439 { 440 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, 441 { 0xc, 0x7, 0x4, 0x6, 0x0, 0x4 }, 442 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 443 }, 444 445 /* voltage swing 2, pre-emphasis 0->1 */ 446 { 447 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, 448 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, 449 }, 450 451 /* voltage swing 3, pre-emphasis 0 */ 452 { 453 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, 454 } 455 }; 456 457 /* pll configurations for link rate R216/R243/R324/R432 */ 458 static struct tx_pll_ctrl tx_pll_ctrl_extra[4] = { 459 { 0x5a, 0x01, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0f, 0x18 }, /* R216 */ 460 { 0x65, 0x01, 0x60, 0x00, 0x10, 0x01, 0x13, 0x18, 0x20, 0x0b }, /* R243 */ 461 { 0x87, 0x01, 0x21, 0x00, 0x00, 0x02, 0x03, 0x08, 0x0e, 0x1a }, /* R324 */ 462 { 0x5a, 0x00, 0x32, 0x00, 0x00, 0x00, 0x01, 0x01, 0x0f, 0x18 }, /* R432 */ 463 }; 464 465 static int rockchip_hdptx_phy_parse_training_table(struct udevice *dev) 466 { 467 int size = sizeof(struct tx_drv_ctrl) * 10; 468 const uint8_t *prop; 469 u8 *buf, *training_table; 470 int i, j; 471 472 prop = dev_read_u8_array_ptr(dev, "training-table", size); 473 if (!prop) 474 return 0; 475 476 buf = kzalloc(size, GFP_KERNEL); 477 if (!buf) 478 return -ENOMEM; 479 480 memcpy(buf, prop, size); 481 482 training_table = buf; 483 484 for (i = 0; i < 4; i++) { 485 for (j = 0; j < 4; j++) { 486 struct tx_drv_ctrl *ctrl; 487 488 if (i + j > 3) 489 continue; 490 491 ctrl = (struct tx_drv_ctrl *)training_table; 492 tx_drv_ctrl_rbr[i][j] = *ctrl; 493 tx_drv_ctrl_hbr[i][j] = *ctrl; 494 tx_drv_ctrl_hbr2[i][j] = *ctrl; 495 training_table += sizeof(*ctrl); 496 } 497 } 498 499 kfree(buf); 500 501 return 0; 502 } 503 504 static inline void rockchip_grf_write(struct regmap *grf, uint reg, uint mask, 505 uint val) 506 { 507 regmap_write(grf, reg, (mask << 16) | (val & mask)); 508 } 509 510 static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, 511 int submode) 512 { 513 return 0; 514 } 515 516 static int rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx, 517 struct phy_configure_opts_dp *dp) 518 { 519 int i; 520 521 if (dp->set_rate) { 522 switch (dp->link_rate) { 523 case 1620: 524 case 2160: 525 case 2430: 526 case 2700: 527 case 3240: 528 case 4320: 529 case 5400: 530 break; 531 default: 532 return -EINVAL; 533 } 534 } 535 536 switch (dp->lanes) { 537 case 1: 538 case 2: 539 case 4: 540 break; 541 default: 542 return -EINVAL; 543 } 544 545 if (dp->set_voltages) { 546 for (i = 0; i < dp->lanes; i++) { 547 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 548 return -EINVAL; 549 550 if (dp->voltage[i] + dp->pre[i] > 3) 551 return -EINVAL; 552 } 553 } 554 555 return 0; 556 } 557 558 static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, 559 struct phy_configure_opts_dp *dp, 560 u8 lane) 561 { 562 const struct tx_drv_ctrl *ctrl; 563 564 switch (dp->link_rate) { 565 case 1620: 566 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; 567 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), 568 LN_TX_SER_40BIT_EN_RBR, 569 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1)); 570 break; 571 case 2160: 572 case 2430: 573 case 2700: 574 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; 575 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), 576 LN_TX_SER_40BIT_EN_HBR, 577 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1)); 578 break; 579 case 3240: 580 case 4320: 581 case 5400: 582 default: 583 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; 584 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), 585 LN_TX_SER_40BIT_EN_HBR2, 586 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1)); 587 break; 588 } 589 590 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c0c), 591 OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL, 592 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL, 0x1) | 593 FIELD_PREP(LN_TX_DRV_LVL_CTRL, 594 ctrl->tx_drv_lvl_ctrl)); 595 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c10), 596 OVRD_LN_TX_DRV_POST_LVL_CTRL | 597 LN_TX_DRV_POST_LVL_CTRL, 598 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL, 0x1) | 599 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL, 600 ctrl->tx_drv_post_lvl_ctrl)); 601 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c18), 602 LN_ANA_TX_DRV_IDRV_IDN_CTRL | 603 LN_ANA_TX_DRV_IDRV_IUP_CTRL | 604 LN_ANA_TX_DRV_ACCDRV_EN, 605 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL, 606 ctrl->ana_tx_drv_idrv_idn_ctrl) | 607 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL, 608 ctrl->ana_tx_drv_idrv_iup_ctrl) | 609 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN, 610 ctrl->ana_tx_drv_accdrv_en)); 611 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c1c), 612 LN_ANA_TX_DRV_ACCDRV_POL_SEL | 613 LN_ANA_TX_DRV_ACCDRV_CTRL, 614 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL, 0x1) | 615 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL, 616 ctrl->ana_tx_drv_accdrv_ctrl)); 617 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c6c), 618 LN_ANA_TX_RESERVED, 619 FIELD_PREP(LN_ANA_TX_RESERVED, 0x1)); 620 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c58), 621 LN_ANA_TX_SER_VREG_GAIN_CTRL, 622 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL, 0x2)); 623 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c40), 624 LN_ANA_TX_SYNC_LOSS_DET_MODE, 625 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE, 0x3)); 626 } 627 628 static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx, 629 struct phy_configure_opts_dp *dp) 630 { 631 u8 lane; 632 u32 status; 633 int ret; 634 635 for (lane = 0; lane < dp->lanes; lane++) 636 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane); 637 638 reset_deassert(&hdptx->lane_reset); 639 640 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 641 status, FIELD_GET(PHY_RDY, status), 642 50, 5000); 643 if (ret) { 644 dev_err(hdptx->dev, "timeout waiting for phy_rdy\n"); 645 return ret; 646 } 647 648 return 0; 649 } 650 651 static bool is_extra_recommended_link_rate(u32 link_rate) 652 { 653 switch (link_rate) { 654 case 2160: 655 case 2430: 656 case 3240: 657 case 4320: 658 return true; 659 } 660 661 return false; 662 } 663 664 static int rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx, 665 struct phy_configure_opts_dp *dp) 666 { 667 u32 bw, status; 668 u32 bw_extra = 0; 669 int ret; 670 671 reset_assert(&hdptx->lane_reset); 672 udelay(10); 673 reset_assert(&hdptx->cmn_reset); 674 udelay(10); 675 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN, 676 FIELD_PREP(PLL_EN, 0x0)); 677 udelay(10); 678 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN, 679 FIELD_PREP(LANE_EN, 0x0)); 680 681 switch (dp->link_rate) { 682 case 1620: 683 bw = DP_BW_RBR; 684 break; 685 case 2160: 686 bw_extra = EDP_BW_2_16; 687 bw = DP_BW_HBR; 688 break; 689 case 2430: 690 bw_extra = EDP_BW_2_43; 691 bw = DP_BW_HBR; 692 break; 693 case 2700: 694 bw = DP_BW_HBR; 695 break; 696 case 3240: 697 bw_extra = EDP_BW_3_24; 698 bw = DP_BW_HBR2; 699 break; 700 case 4320: 701 bw_extra = EDP_BW_4_32; 702 bw = DP_BW_HBR2; 703 break; 704 case 5400: 705 bw = DP_BW_HBR2; 706 break; 707 default: 708 return -EINVAL; 709 } 710 711 if (is_extra_recommended_link_rate(dp->link_rate)) { 712 const struct tx_pll_ctrl *pll_ctrl = &tx_pll_ctrl_extra[bw_extra]; 713 714 regmap_write(hdptx->regmap, 0x0144 + bw * 0x4, 715 FIELD_PREP(ROPLL_PMS_MDIV, pll_ctrl->mdiv)); 716 regmap_write(hdptx->regmap, 0x0180 + bw * 0x4, 717 FIELD_PREP(ROPLL_SDM_DENOMINATOR, pll_ctrl->sdm_denominator)); 718 regmap_write(hdptx->regmap, 0x0194 + bw * 0x4, 719 FIELD_PREP(ROPLL_SDM_NUMERATOR, pll_ctrl->sdm_numerator)); 720 regmap_write(hdptx->regmap, 0x01b0 + bw * 0x4, 721 FIELD_PREP(ROPLL_SDC_NUMERATOR, pll_ctrl->sdc_numerator)); 722 regmap_write(hdptx->regmap, 0x01c0 + bw * 0x4, 723 FIELD_PREP(ROPLL_SDC_DENOMINATOR, pll_ctrl->sdc_denominator)); 724 725 if (bw == DP_BW_RBR) { 726 regmap_update_bits(hdptx->regmap, 0x0168, ROPLL_PMS_SDIV_RBR, 727 FIELD_PREP(ROPLL_PMS_SDIV_RBR, pll_ctrl->sdiv)); 728 regmap_update_bits(hdptx->regmap, 0x0190, ROPLL_SDM_NUMERATOR_SIGN_RBR, 729 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 730 pll_ctrl->sdm_numerator_sign)); 731 regmap_update_bits(hdptx->regmap, 0x01a4, ROPLL_SDC_N_RBR, 732 FIELD_PREP(ROPLL_SDC_N_RBR, pll_ctrl->sdc_clock_div)); 733 } else if (bw == DP_BW_HBR) { 734 regmap_update_bits(hdptx->regmap, 0x0168, ROPLL_PMS_SDIV_HBR, 735 FIELD_PREP(ROPLL_PMS_SDIV_HBR, pll_ctrl->sdiv)); 736 regmap_update_bits(hdptx->regmap, 0x0190, ROPLL_SDM_NUMERATOR_SIGN_HBR, 737 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 738 pll_ctrl->sdm_numerator_sign)); 739 regmap_update_bits(hdptx->regmap, 0x01a8, ROPLL_SDC_N_HBR, 740 FIELD_PREP(ROPLL_SDC_N_HBR, pll_ctrl->sdc_clock_div)); 741 } else { 742 regmap_update_bits(hdptx->regmap, 0x016c, ROPLL_PMS_SDIV_HBR2, 743 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, pll_ctrl->sdiv)); 744 regmap_update_bits(hdptx->regmap, 0x0190, ROPLL_SDM_NUMERATOR_SIGN_HBR2, 745 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 746 pll_ctrl->sdm_numerator_sign)); 747 regmap_update_bits(hdptx->regmap, 0x01a8, ROPLL_SDC_N_HBR2, 748 FIELD_PREP(ROPLL_SDC_N_HBR2, pll_ctrl->sdc_clock_div)); 749 } 750 } 751 752 regmap_update_bits(hdptx->regmap, 0x0254, DP_TX_LINK_BW, 753 FIELD_PREP(DP_TX_LINK_BW, bw)); 754 755 if (dp->ssc) { 756 regmap_update_bits(hdptx->regmap, 0x01d0, 757 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 758 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 759 FIELD_PREP(ROPLL_SSC_EN, 0x1)); 760 if (is_extra_recommended_link_rate(dp->link_rate)) { 761 const struct tx_pll_ctrl *pll_ctrl = &tx_pll_ctrl_extra[bw_extra]; 762 763 regmap_write(hdptx->regmap, 0x01d4, 764 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 765 pll_ctrl->ssc_deviation)); 766 regmap_update_bits(hdptx->regmap, 0x01d8, 767 ANA_ROPLL_SSC_FM_FREQ, 768 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 769 pll_ctrl->ssc_freq)); 770 } else { 771 regmap_write(hdptx->regmap, 0x01d4, 772 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0xc)); 773 regmap_update_bits(hdptx->regmap, 0x01d8, 774 ANA_ROPLL_SSC_FM_FREQ, 775 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0x1f)); 776 } 777 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN, 778 FIELD_PREP(SSC_EN, 0x2)); 779 } else { 780 regmap_update_bits(hdptx->regmap, 0x01d0, 781 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 782 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 783 FIELD_PREP(ROPLL_SSC_EN, 0x0)); 784 regmap_update_bits(hdptx->regmap, 0x01d4, 785 ANA_ROPLL_SSC_FM_DEVIATION, 786 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0x20)); 787 regmap_update_bits(hdptx->regmap, 0x01d8, 788 ANA_ROPLL_SSC_FM_FREQ, 789 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0xc)); 790 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN, 791 FIELD_PREP(SSC_EN, 0x0)); 792 } 793 794 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN, 795 FIELD_PREP(PLL_EN, 0x1)); 796 udelay(10); 797 reset_deassert(&hdptx->cmn_reset); 798 udelay(10); 799 800 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 801 status, FIELD_GET(PLL_LOCK_DONE, status), 802 50, 1000); 803 if (ret) { 804 dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n"); 805 return ret; 806 } 807 808 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN, 809 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0))); 810 811 return 0; 812 } 813 814 static int rockchip_hdptx_phy_configure(struct phy *phy, 815 union phy_configure_opts *opts) 816 { 817 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 818 enum phy_mode mode = generic_phy_get_mode(phy); 819 int ret; 820 821 if (mode != PHY_MODE_DP) 822 return -EINVAL; 823 824 ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp); 825 if (ret) { 826 dev_err(hdptx->dev, "invalid params for phy configure\n"); 827 return ret; 828 } 829 830 if (opts->dp.set_rate) { 831 ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp); 832 if (ret) { 833 dev_err(hdptx->dev, "failed to set rate: %d\n", ret); 834 return ret; 835 } 836 } 837 838 if (opts->dp.set_voltages) { 839 ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp); 840 if (ret) { 841 dev_err(hdptx->dev, "failed to set voltages: %d\n", 842 ret); 843 return ret; 844 } 845 } 846 847 return 0; 848 } 849 850 static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx) 851 { 852 regmap_update_bits(hdptx->regmap, 0x0020, OVRD_LCPLL_EN | LCPLL_EN, 853 FIELD_PREP(OVRD_LCPLL_EN, 0x1) | 854 FIELD_PREP(LCPLL_EN, 0x0)); 855 regmap_update_bits(hdptx->regmap, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN, 856 FIELD_PREP(OVRD_ROPLL_EN, 0x1) | 857 FIELD_PREP(ROPLL_EN, 0x1)); 858 regmap_update_bits(hdptx->regmap, 0x0138, ANA_ROPLL_PI_EN, 859 FIELD_PREP(ANA_ROPLL_PI_EN, 0x1)); 860 regmap_write(hdptx->regmap, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87)); 861 regmap_write(hdptx->regmap, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 862 regmap_write(hdptx->regmap, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 863 regmap_write(hdptx->regmap, 0x0154, 864 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x87)); 865 regmap_write(hdptx->regmap, 0x0158, 866 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 867 regmap_write(hdptx->regmap, 0x015c, 868 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 869 regmap_write(hdptx->regmap, 0x0164, 870 FIELD_PREP(ANA_ROPLL_PMS_PDIV, 0x1) | 871 FIELD_PREP(ANA_ROPLL_PMS_REFDIV, 0x1)); 872 regmap_write(hdptx->regmap, 0x0168, 873 FIELD_PREP(ROPLL_PMS_SDIV_RBR, 0x3) | 874 FIELD_PREP(ROPLL_PMS_SDIV_HBR, 0x1)); 875 regmap_update_bits(hdptx->regmap, 0x016c, ROPLL_PMS_SDIV_HBR2, 876 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, 0x0)); 877 regmap_update_bits(hdptx->regmap, 0x0178, ANA_ROPLL_SDM_EN, 878 FIELD_PREP(ANA_ROPLL_SDM_EN, 0x1)); 879 regmap_update_bits(hdptx->regmap, 0x0178, 880 OVRD_ROPLL_SDM_RSTN | ROPLL_SDM_RSTN, 881 FIELD_PREP(OVRD_ROPLL_SDM_RSTN, 0x1) | 882 FIELD_PREP(ROPLL_SDM_RSTN, 0x1)); 883 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR, 884 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_RBR, 0x1)); 885 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR, 886 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR, 0x1)); 887 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2, 888 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR2, 0x1)); 889 regmap_update_bits(hdptx->regmap, 0x017c, 890 OVRD_ROPLL_SDC_RSTN | ROPLL_SDC_RSTN, 891 FIELD_PREP(OVRD_ROPLL_SDC_RSTN, 0x1) | 892 FIELD_PREP(ROPLL_SDC_RSTN, 0x1)); 893 regmap_write(hdptx->regmap, 0x0180, 894 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x21)); 895 regmap_write(hdptx->regmap, 0x0184, 896 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 897 regmap_write(hdptx->regmap, 0x0188, 898 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 899 regmap_update_bits(hdptx->regmap, 0x0190, 900 ROPLL_SDM_NUMERATOR_SIGN_RBR | 901 ROPLL_SDM_NUMERATOR_SIGN_HBR | 902 ROPLL_SDM_NUMERATOR_SIGN_HBR2, 903 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 0x0) | 904 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 0x1) | 905 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 0x1)); 906 regmap_write(hdptx->regmap, 0x0194, 907 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0x0)); 908 regmap_write(hdptx->regmap, 0x0198, 909 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 910 regmap_write(hdptx->regmap, 0x019c, 911 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 912 regmap_update_bits(hdptx->regmap, 0x01a4, ROPLL_SDC_N_RBR, 913 FIELD_PREP(ROPLL_SDC_N_RBR, 0x2)); 914 regmap_update_bits(hdptx->regmap, 0x01a8, 915 ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2, 916 FIELD_PREP(ROPLL_SDC_N_HBR, 0x2) | 917 FIELD_PREP(ROPLL_SDC_N_HBR2, 0x2)); 918 regmap_write(hdptx->regmap, 0x01b0, 919 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3)); 920 regmap_write(hdptx->regmap, 0x01b4, 921 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 922 regmap_write(hdptx->regmap, 0x01b8, 923 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 924 regmap_write(hdptx->regmap, 0x01c0, 925 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x8)); 926 regmap_write(hdptx->regmap, 0x01c4, 927 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 928 regmap_write(hdptx->regmap, 0x01c8, 929 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 930 regmap_update_bits(hdptx->regmap, 0x01d0, 931 OVRD_ROPLL_SDC_NDIV_RSTN | ROPLL_SDC_NDIV_RSTN, 932 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN, 0x1) | 933 FIELD_PREP(ROPLL_SDC_NDIV_RSTN, 0x1)); 934 regmap_update_bits(hdptx->regmap, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL, 935 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL, 0x1)); 936 regmap_update_bits(hdptx->regmap, 0x0118, 937 ROPLL_ANA_CPP_CTRL_COARSE | ROPLL_ANA_CPP_CTRL_FINE, 938 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE, 0xe) | 939 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE, 0xe)); 940 regmap_update_bits(hdptx->regmap, 0x011c, 941 ROPLL_ANA_LPF_C_SEL_COARSE | 942 ROPLL_ANA_LPF_C_SEL_FINE, 943 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE, 0x4) | 944 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE, 0x4)); 945 regmap_update_bits(hdptx->regmap, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL, 946 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL, 0x0)); 947 regmap_update_bits(hdptx->regmap, 0x025c, DIG_CLK_SEL, 948 FIELD_PREP(DIG_CLK_SEL, 0x1)); 949 regmap_update_bits(hdptx->regmap, 0x021c, ANA_PLL_TX_HS_CLK_EN, 950 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN, 0x1)); 951 regmap_update_bits(hdptx->regmap, 0x0204, 952 ANA_PLL_CD_HSCLK_EAST_EN | ANA_PLL_CD_HSCLK_WEST_EN, 953 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN, 0x1) | 954 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN, 0x0)); 955 regmap_update_bits(hdptx->regmap, 0x0264, CMN_ROPLL_ALONE_MODE, 956 FIELD_PREP(CMN_ROPLL_ALONE_MODE, 0x1)); 957 regmap_update_bits(hdptx->regmap, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL, 958 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL, 0x4)); 959 regmap_update_bits(hdptx->regmap, 0x00f0, ANA_LCPLL_RESERVED7, 960 FIELD_PREP(ANA_LCPLL_RESERVED7, 0x1)); 961 regmap_update_bits(hdptx->regmap, 0x020c, ANA_PLL_CD_VREG_ICTRL, 962 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL, 0x1)); 963 regmap_update_bits(hdptx->regmap, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE, 964 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE, 0x3)); 965 regmap_update_bits(hdptx->regmap, 0x0210, PLL_LCRO_CLK_SEL, 966 FIELD_PREP(PLL_LCRO_CLK_SEL, 0x1)); 967 regmap_update_bits(hdptx->regmap, 0x0268, HS_SPEED_SEL, 968 FIELD_PREP(HS_SPEED_SEL, 0x1)); 969 regmap_update_bits(hdptx->regmap, 0x026c, LS_SPEED_SEL, 970 FIELD_PREP(LS_SPEED_SEL, 0x1)); 971 } 972 973 static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx) 974 { 975 u32 status; 976 int ret; 977 978 regmap_update_bits(hdptx->regmap, 0x0414, ANA_SB_TX_HLVL_PROG, 979 FIELD_PREP(ANA_SB_TX_HLVL_PROG, 0x7)); 980 regmap_update_bits(hdptx->regmap, 0x0418, ANA_SB_TX_LLVL_PROG, 981 FIELD_PREP(ANA_SB_TX_LLVL_PROG, 0x7)); 982 regmap_update_bits(hdptx->regmap, 0x044c, 983 SB_RX_RCAL_OPT_CODE | SB_RX_RTERM_CTRL, 984 FIELD_PREP(SB_RX_RCAL_OPT_CODE, 0x1) | 985 FIELD_PREP(SB_RX_RTERM_CTRL, 0x3)); 986 regmap_update_bits(hdptx->regmap, 0x0450, 987 SB_TG_SB_EN_DELAY_TIME | SB_TG_RXTERN_EN_DELAY_TIME, 988 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME, 0x2) | 989 FIELD_PREP(SB_TG_RXTERN_EN_DELAY_TIME, 0x2)); 990 regmap_update_bits(hdptx->regmap, 0x0454, 991 SB_READY_DELAY_TIME | SB_TG_OSC_EN_DELAY_TIME, 992 FIELD_PREP(SB_READY_DELAY_TIME, 0x2) | 993 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME, 0x2)); 994 regmap_update_bits(hdptx->regmap, 0x0458, 995 SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 996 FIELD_PREP(SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 0x2)); 997 regmap_update_bits(hdptx->regmap, 0x045c, 998 SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 999 FIELD_PREP(SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 0x4)); 1000 regmap_update_bits(hdptx->regmap, 0x0460, 1001 SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 1002 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 0xa)); 1003 regmap_update_bits(hdptx->regmap, 0x0468, SB_TG_CNT_RUN_NO_7_0, 1004 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0, 0x3)); 1005 regmap_update_bits(hdptx->regmap, 0x046c, 1006 SB_EARC_SIG_DET_BYPASS | SB_AFC_TOL, 1007 FIELD_PREP(SB_EARC_SIG_DET_BYPASS, 0x1) | 1008 FIELD_PREP(SB_AFC_TOL, 0x3)); 1009 regmap_update_bits(hdptx->regmap, 0x0470, SB_AFC_STB_NUM, 1010 FIELD_PREP(SB_AFC_STB_NUM, 0x4)); 1011 regmap_update_bits(hdptx->regmap, 0x0474, SB_TG_OSC_CNT_MIN, 1012 FIELD_PREP(SB_TG_OSC_CNT_MIN, 0x67)); 1013 regmap_update_bits(hdptx->regmap, 0x0478, SB_TG_OSC_CNT_MAX, 1014 FIELD_PREP(SB_TG_OSC_CNT_MAX, 0x6a)); 1015 regmap_update_bits(hdptx->regmap, 0x047c, SB_PWM_AFC_CTRL, 1016 FIELD_PREP(SB_PWM_AFC_CTRL, 0x5)); 1017 regmap_update_bits(hdptx->regmap, 0x0434, ANA_SB_DMRX_LPBK_DATA, 1018 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA, 0x1)); 1019 regmap_update_bits(hdptx->regmap, 0x0440, 1020 ANA_SB_VREG_OUT_SEL | ANA_SB_VREG_REF_SEL, 1021 FIELD_PREP(ANA_SB_VREG_OUT_SEL, 0x1) | 1022 FIELD_PREP(ANA_SB_VREG_REF_SEL, 0x1)); 1023 regmap_update_bits(hdptx->regmap, 0x043c, ANA_SB_VREG_GAIN_CTRL, 1024 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL, 0x0)); 1025 regmap_update_bits(hdptx->regmap, 0x0408, ANA_SB_RXTERM_OFFSP, 1026 FIELD_PREP(ANA_SB_RXTERM_OFFSP, 0x3)); 1027 regmap_update_bits(hdptx->regmap, 0x040c, ANA_SB_RXTERM_OFFSN, 1028 FIELD_PREP(ANA_SB_RXTERM_OFFSN, 0x3)); 1029 regmap_update_bits(hdptx->regmap, 0x047c, SB_RCAL_RSTN, 1030 FIELD_PREP(SB_RCAL_RSTN, 0x1)); 1031 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN, 1032 FIELD_PREP(SB_AUX_EN, 0x1)); 1033 regmap_update_bits(hdptx->regmap, 0x0480, SB_AUX_EN_IN, 1034 FIELD_PREP(SB_AUX_EN_IN, 0x1)); 1035 regmap_update_bits(hdptx->regmap, 0x040c, OVRD_SB_RX_RESCAL_DONE, 1036 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE, 0x1)); 1037 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_EN, 1038 FIELD_PREP(OVRD_SB_EN, 0x1)); 1039 regmap_update_bits(hdptx->regmap, 0x0408, OVRD_SB_RXTERM_EN, 1040 FIELD_PREP(OVRD_SB_RXTERM_EN, 0x1)); 1041 regmap_update_bits(hdptx->regmap, 0x043c, OVRD_SB_VREG_EN, 1042 FIELD_PREP(OVRD_SB_VREG_EN, 0x1)); 1043 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_AUX_EN, 1044 FIELD_PREP(OVRD_SB_AUX_EN, 0x1)); 1045 1046 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN, 1047 FIELD_PREP(BGR_EN, 0x1)); 1048 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN, 1049 FIELD_PREP(BIAS_EN, 0x1)); 1050 udelay(10); 1051 reset_deassert(&hdptx->init_reset); 1052 udelay(1000); 1053 reset_deassert(&hdptx->cmn_reset); 1054 udelay(20); 1055 1056 regmap_update_bits(hdptx->regmap, 0x040c, SB_RX_RESCAL_DONE, 1057 FIELD_PREP(SB_RX_RESCAL_DONE, 0x1)); 1058 udelay(100); 1059 regmap_update_bits(hdptx->regmap, 0x0410, SB_EN, 1060 FIELD_PREP(SB_EN, 0x1)); 1061 udelay(100); 1062 regmap_update_bits(hdptx->regmap, 0x0408, SB_RXRERM_EN, 1063 FIELD_PREP(SB_RXRERM_EN, 0x1)); 1064 udelay(10); 1065 regmap_update_bits(hdptx->regmap, 0x043c, SB_VREG_EN, 1066 FIELD_PREP(SB_VREG_EN, 0x1)); 1067 udelay(10); 1068 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN, 1069 FIELD_PREP(SB_AUX_EN, 0x1)); 1070 udelay(100); 1071 1072 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 1073 status, FIELD_GET(SB_RDY, status), 1074 50, 1000); 1075 if (ret) { 1076 dev_err(hdptx->dev, "timeout waiting for sb_rdy\n"); 1077 return ret; 1078 } 1079 1080 return 0; 1081 } 1082 1083 static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx) 1084 { 1085 u32 lane; 1086 1087 reset_assert(&hdptx->lane_reset); 1088 reset_assert(&hdptx->cmn_reset); 1089 reset_assert(&hdptx->init_reset); 1090 1091 reset_assert(&hdptx->apb_reset); 1092 udelay(10); 1093 reset_deassert(&hdptx->apb_reset); 1094 1095 for (lane = 0; lane < 4; lane++) 1096 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c04), 1097 OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN, 1098 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN, 1) | 1099 FIELD_PREP(LN_TX_DRV_EI_EN, 0)); 1100 1101 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN, 1102 FIELD_PREP(PLL_EN, 0)); 1103 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN, 1104 FIELD_PREP(BIAS_EN, 0)); 1105 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN, 1106 FIELD_PREP(BGR_EN, 0)); 1107 } 1108 1109 static int rockchip_hdptx_phy_power_on(struct phy *phy) 1110 { 1111 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 1112 enum phy_mode mode = generic_phy_get_mode(phy); 1113 u32 lane; 1114 1115 rockchip_hdptx_phy_reset(hdptx); 1116 1117 for (lane = 0; lane < 4; lane++) { 1118 u32 invert = hdptx->lane_polarity_invert[lane]; 1119 1120 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c78), 1121 LN_POLARITY_INV | LN_LANE_MODE, 1122 FIELD_PREP(LN_POLARITY_INV, invert) | 1123 FIELD_PREP(LN_LANE_MODE, 1)); 1124 } 1125 1126 if (mode == PHY_MODE_DP) { 1127 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, 1128 HDPTX_MODE_SEL, 1129 FIELD_PREP(HDPTX_MODE_SEL, 0x1)); 1130 1131 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL, 1132 FIELD_PREP(PROTOCOL_SEL, 0x0)); 1133 regmap_update_bits(hdptx->regmap, 0x0818, DATA_BUS_WIDTH, 1134 FIELD_PREP(DATA_BUS_WIDTH, 0x1)); 1135 regmap_update_bits(hdptx->regmap, 0x0818, BUS_WIDTH_SEL, 1136 FIELD_PREP(BUS_WIDTH_SEL, 0x0)); 1137 1138 rockchip_hdptx_phy_dp_pll_init(hdptx); 1139 rockchip_hdptx_phy_dp_aux_init(hdptx); 1140 } else { 1141 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, 1142 HDPTX_MODE_SEL, 1143 FIELD_PREP(HDPTX_MODE_SEL, 0x0)); 1144 1145 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL, 1146 FIELD_PREP(PROTOCOL_SEL, 0x1)); 1147 } 1148 1149 return 0; 1150 } 1151 1152 static int rockchip_hdptx_phy_power_off(struct phy *phy) 1153 { 1154 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 1155 1156 rockchip_hdptx_phy_reset(hdptx); 1157 1158 return 0; 1159 } 1160 1161 static const struct phy_ops rockchip_hdptx_phy_ops = { 1162 .set_mode = rockchip_hdptx_phy_set_mode, 1163 .configure = rockchip_hdptx_phy_configure, 1164 .power_on = rockchip_hdptx_phy_power_on, 1165 .power_off = rockchip_hdptx_phy_power_off, 1166 }; 1167 1168 static int rockchip_hdptx_phy_probe(struct udevice *dev) 1169 { 1170 struct rockchip_hdptx_phy *hdptx = dev_get_priv(dev); 1171 struct udevice *syscon; 1172 u32 prop[4]; 1173 int ret; 1174 1175 ret = regmap_init_mem(dev, &hdptx->regmap); 1176 if (ret) 1177 return ret; 1178 1179 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1180 &syscon); 1181 if (ret) 1182 return ret; 1183 1184 hdptx->grf = syscon_get_regmap(syscon); 1185 if (IS_ERR(hdptx->grf)) { 1186 ret = PTR_ERR(hdptx->grf); 1187 dev_err(dev, "unable to find regmap: %d\n", ret); 1188 return ret; 1189 } 1190 1191 hdptx->dev = dev; 1192 1193 ret = reset_get_by_name(dev, "apb", &hdptx->apb_reset); 1194 if (ret < 0) { 1195 dev_err(dev, "failed to get apb reset: %d\n", ret); 1196 return ret; 1197 } 1198 1199 ret = reset_get_by_name(dev, "init", &hdptx->init_reset); 1200 if (ret < 0) { 1201 dev_err(dev, "failed to get init reset: %d\n", ret); 1202 return ret; 1203 } 1204 1205 ret = reset_get_by_name(dev, "cmn", &hdptx->cmn_reset); 1206 if (ret < 0) { 1207 dev_err(dev, "failed to get cmn reset: %d\n", ret); 1208 return ret; 1209 } 1210 1211 ret = reset_get_by_name(dev, "lane", &hdptx->lane_reset); 1212 if (ret < 0) { 1213 dev_err(dev, "failed to get lane reset: %d\n", ret); 1214 return ret; 1215 } 1216 1217 ret = rockchip_hdptx_phy_parse_training_table(dev); 1218 if (ret) { 1219 dev_err(dev, "failed to parse training table: %d\n", ret); 1220 return ret; 1221 } 1222 1223 if (!dev_read_u32_array(dev, "lane-polarity-invert", prop, ARRAY_SIZE(prop))) { 1224 hdptx->lane_polarity_invert[0] = prop[0]; 1225 hdptx->lane_polarity_invert[1] = prop[1]; 1226 hdptx->lane_polarity_invert[2] = prop[2]; 1227 hdptx->lane_polarity_invert[3] = prop[3]; 1228 } 1229 1230 return 0; 1231 } 1232 1233 static const struct udevice_id rockchip_hdptx_phy_ids[] = { 1234 { .compatible = "rockchip,rk3588-hdptx-phy", }, 1235 {} 1236 }; 1237 1238 U_BOOT_DRIVER(rockchip_hdptx_phy) = { 1239 .name = "rockchip_hdptx_phy", 1240 .id = UCLASS_PHY, 1241 .ops = &rockchip_hdptx_phy_ops, 1242 .of_match = rockchip_hdptx_phy_ids, 1243 .probe = rockchip_hdptx_phy_probe, 1244 .priv_auto_alloc_size = sizeof(struct rockchip_hdptx_phy), 1245 }; 1246