1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip HDMI/DP Combo PHY with Samsung IP block 4 * 5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <reset.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <linux/bitfield.h> 16 #include <linux/rational.h> 17 #include <linux/iopoll.h> 18 #include <asm/arch/clock.h> 19 #include <dm/lists.h> 20 #include <dm/of_access.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_phy.h" 25 26 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 27 28 #define GRF_HDPTX_CON0 0x00 29 #define HDPTX_I_PLL_EN BIT(7) 30 #define HDPTX_I_BIAS_EN BIT(6) 31 #define HDPTX_I_BGR_EN BIT(5) 32 #define GRF_HDPTX_STATUS 0x80 33 #define HDPTX_O_PLL_LOCK_DONE BIT(3) 34 #define HDPTX_O_PHY_CLK_RDY BIT(2) 35 #define HDPTX_O_PHY_RDY BIT(1) 36 #define HDPTX_O_SB_RDY BIT(0) 37 38 #define CMN_REG0000 0x0000 39 #define CMN_REG0001 0x0004 40 #define CMN_REG0002 0x0008 41 #define CMN_REG0003 0x000C 42 #define CMN_REG0004 0x0010 43 #define CMN_REG0005 0x0014 44 #define CMN_REG0006 0x0018 45 #define CMN_REG0007 0x001C 46 #define CMN_REG0008 0x0020 47 #define LCPLL_EN_MASK BIT(6) 48 #define LCPLL_EN(x) UPDATE(x, 4, 4) 49 #define LCPLL_LCVCO_MODE_EN_MASK BIT(4) 50 #define LCPLL_LCVCO_MODE_EN(x) UPDATE(x, 4, 4) 51 #define CMN_REG0009 0x0024 52 #define CMN_REG000A 0x0028 53 #define CMN_REG000B 0x002C 54 #define CMN_REG000C 0x0030 55 #define CMN_REG000D 0x0034 56 #define CMN_REG000E 0x0038 57 #define CMN_REG000F 0x003C 58 #define CMN_REG0010 0x0040 59 #define CMN_REG0011 0x0044 60 #define CMN_REG0012 0x0048 61 #define CMN_REG0013 0x004C 62 #define CMN_REG0014 0x0050 63 #define CMN_REG0015 0x0054 64 #define CMN_REG0016 0x0058 65 #define CMN_REG0017 0x005C 66 #define CMN_REG0018 0x0060 67 #define CMN_REG0019 0x0064 68 #define CMN_REG001A 0x0068 69 #define CMN_REG001B 0x006C 70 #define CMN_REG001C 0x0070 71 #define CMN_REG001D 0x0074 72 #define CMN_REG001E 0x0078 73 #define LCPLL_PI_EN_MASK BIT(5) 74 #define LCPLL_PI_EN(x) UPDATE(x, 5, 5) 75 #define LCPLL_100M_CLK_EN_MASK BIT(0) 76 #define LCPLL_100M_CLK_EN(x) UPDATE(x, 0, 0) 77 #define CMN_REG001F 0x007C 78 #define CMN_REG0020 0x0080 79 #define CMN_REG0021 0x0084 80 #define CMN_REG0022 0x0088 81 #define CMN_REG0023 0x008C 82 #define CMN_REG0024 0x0090 83 #define CMN_REG0025 0x0094 84 #define LCPLL_PMS_IQDIV_RSTN BIT(4) 85 #define CMN_REG0026 0x0098 86 #define CMN_REG0027 0x009C 87 #define CMN_REG0028 0x00A0 88 #define LCPLL_SDC_FRAC_EN BIT(2) 89 #define LCPLL_SDC_FRAC_RSTN BIT(0) 90 #define CMN_REG0029 0x00A4 91 #define CMN_REG002A 0x00A8 92 #define CMN_REG002B 0x00AC 93 #define CMN_REG002C 0x00B0 94 #define CMN_REG002D 0x00B4 95 #define LCPLL_SDC_N_MASK GENMASK(3, 1) 96 #define LCPLL_SDC_N(x) UPDATE(x, 3, 1) 97 #define CMN_REG002E 0x00B8 98 #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0) 99 #define LCPLL_SDC_NUMBERATOR(x) UPDATE(x, 5, 0) 100 #define CMN_REG002F 0x00BC 101 #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2) 102 #define LCPLL_SDC_DENOMINATOR(x) UPDATE(x, 7, 2) 103 #define LCPLL_SDC_NDIV_RSTN BIT(0) 104 #define CMN_REG0030 0x00C0 105 #define CMN_REG0031 0x00C4 106 #define CMN_REG0032 0x00C8 107 #define CMN_REG0033 0x00CC 108 #define CMN_REG0034 0x00D0 109 #define CMN_REG0035 0x00D4 110 #define CMN_REG0036 0x00D8 111 #define CMN_REG0037 0x00DC 112 #define CMN_REG0038 0x00E0 113 #define CMN_REG0039 0x00E4 114 #define CMN_REG003A 0x00E8 115 #define CMN_REG003B 0x00EC 116 #define CMN_REG003C 0x00F0 117 #define CMN_REG003D 0x00F4 118 #define ROPLL_LCVCO_EN BIT(4) 119 #define CMN_REG003E 0x00F8 120 #define CMN_REG003F 0x00FC 121 #define CMN_REG0040 0x0100 122 #define CMN_REG0041 0x0104 123 #define CMN_REG0042 0x0108 124 #define CMN_REG0043 0x010C 125 #define CMN_REG0044 0x0110 126 #define CMN_REG0045 0x0114 127 #define CMN_REG0046 0x0118 128 #define CMN_REG0047 0x011C 129 #define CMN_REG0048 0x0120 130 #define CMN_REG0049 0x0124 131 #define CMN_REG004A 0x0128 132 #define CMN_REG004B 0x012C 133 #define CMN_REG004C 0x0130 134 #define CMN_REG004D 0x0134 135 #define CMN_REG004E 0x0138 136 #define ROPLL_PI_EN BIT(5) 137 #define CMN_REG004F 0x013C 138 #define CMN_REG0050 0x0140 139 #define CMN_REG0051 0x0144 140 #define CMN_REG0052 0x0148 141 #define CMN_REG0053 0x014C 142 #define CMN_REG0054 0x0150 143 #define CMN_REG0055 0x0154 144 #define CMN_REG0056 0x0158 145 #define CMN_REG0057 0x015C 146 #define CMN_REG0058 0x0160 147 #define CMN_REG0059 0x0164 148 #define CMN_REG005A 0x0168 149 #define CMN_REG005B 0x016C 150 #define CMN_REG005C 0x0170 151 #define ROPLL_PMS_IQDIV_RSTN BIT(5) 152 #define CMN_REG005D 0x0174 153 #define CMN_REG005E 0x0178 154 #define ROPLL_SDM_EN_MASK BIT(6) 155 #define ROPLL_SDM_EN(x) UPDATE(x, 6, 6) 156 #define ROPLL_SDM_FRAC_EN_RBR BIT(3) 157 #define ROPLL_SDM_FRAC_EN_HBR BIT(2) 158 #define ROPLL_SDM_FRAC_EN_HBR2 BIT(1) 159 #define ROPLL_SDM_FRAC_EN_HBR3 BIT(0) 160 #define CMN_REG005F 0x017C 161 #define CMN_REG0060 0x0180 162 #define CMN_REG0061 0x0184 163 #define CMN_REG0062 0x0188 164 #define CMN_REG0063 0x018C 165 #define CMN_REG0064 0x0190 166 #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3) 167 #define ROPLL_SDM_NUM_SIGN_RBR(x) UPDATE(x, 3, 3) 168 #define CMN_REG0065 0x0194 169 #define CMN_REG0066 0x0198 170 #define CMN_REG0067 0x019C 171 #define CMN_REG0068 0x01A0 172 #define CMN_REG0069 0x01A4 173 #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0) 174 #define ROPLL_SDC_N_RBR(x) UPDATE(x, 2, 0) 175 #define CMN_REG006A 0x01A8 176 #define CMN_REG006B 0x01AC 177 #define CMN_REG006C 0x01B0 178 #define CMN_REG006D 0x01B4 179 #define CMN_REG006E 0x01B8 180 #define CMN_REG006F 0x01BC 181 #define CMN_REG0070 0x01C0 182 #define CMN_REG0071 0x01C4 183 #define CMN_REG0072 0x01C8 184 #define CMN_REG0073 0x01CC 185 #define CMN_REG0074 0x01D0 186 #define ROPLL_SDC_NDIV_RSTN BIT(2) 187 #define ROPLL_SSC_EN BIT(0) 188 #define CMN_REG0075 0x01D4 189 #define CMN_REG0076 0x01D8 190 #define CMN_REG0077 0x01DC 191 #define CMN_REG0078 0x01E0 192 #define CMN_REG0079 0x01E4 193 #define CMN_REG007A 0x01E8 194 #define CMN_REG007B 0x01EC 195 #define CMN_REG007C 0x01F0 196 #define CMN_REG007D 0x01F4 197 #define CMN_REG007E 0x01F8 198 #define CMN_REG007F 0x01FC 199 #define CMN_REG0080 0x0200 200 #define CMN_REG0081 0x0204 201 #define OVRD_PLL_CD_CLK_EN BIT(8) 202 #define PLL_CD_HSCLK_EAST_EN BIT(0) 203 #define CMN_REG0082 0x0208 204 #define CMN_REG0083 0x020C 205 #define CMN_REG0084 0x0210 206 #define CMN_REG0085 0x0214 207 #define CMN_REG0086 0x0218 208 #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) 209 #define PLL_PCG_POSTDIV_SEL(x) UPDATE(x, 7, 4) 210 #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) 211 #define PLL_PCG_CLK_SEL(x) UPDATE(x, 3, 1) 212 #define PLL_PCG_CLK_EN BIT(0) 213 #define CMN_REG0087 0x021C 214 #define PLL_FRL_MODE_EN BIT(3) 215 #define PLL_TX_HS_CLK_EN BIT(2) 216 #define CMN_REG0088 0x0220 217 #define CMN_REG0089 0x0224 218 #define LCPLL_ALONE_MODE BIT(1) 219 #define CMN_REG008A 0x0228 220 #define CMN_REG008B 0x022C 221 #define CMN_REG008C 0x0230 222 #define CMN_REG008D 0x0234 223 #define CMN_REG008E 0x0238 224 #define CMN_REG008F 0x023C 225 #define CMN_REG0090 0x0240 226 #define CMN_REG0091 0x0244 227 #define CMN_REG0092 0x0248 228 #define CMN_REG0093 0x024C 229 #define CMN_REG0094 0x0250 230 #define CMN_REG0095 0x0254 231 #define CMN_REG0096 0x0258 232 #define CMN_REG0097 0x025C 233 #define DIG_CLK_SEL BIT(1) 234 #define ROPLL_REF BIT(1) 235 #define LCPLL_REF 0 236 #define CMN_REG0098 0x0260 237 #define CMN_REG0099 0x0264 238 #define CMN_ROPLL_ALONE_MODE BIT(2) 239 #define ROPLL_ALONE_MODE BIT(2) 240 #define CMN_REG009A 0x0268 241 #define HS_SPEED_SEL BIT(0) 242 #define DIV_10_CLOCK BIT(0) 243 #define CMN_REG009B 0x026C 244 #define IS_SPEED_SEL BIT(4) 245 #define LINK_SYMBOL_CLOCK BIT(4) 246 #define LINK_SYMBOL_CLOCK1_2 0 247 #define CMN_REG009C 0x0270 248 #define CMN_REG009D 0x0274 249 #define CMN_REG009E 0x0278 250 #define CMN_REG009F 0x027C 251 #define CMN_REG00A0 0x0280 252 #define CMN_REG00A1 0x0284 253 #define CMN_REG00A2 0x0288 254 #define CMN_REG00A3 0x028C 255 #define CMN_REG00AD 0x0290 256 #define CMN_REG00A5 0x0294 257 #define CMN_REG00A6 0x0298 258 #define CMN_REG00A7 0x029C 259 #define SB_REG0100 0x0400 260 #define SB_REG0101 0x0404 261 #define SB_REG0102 0x0408 262 #define OVRD_SB_RXTERM_EN_MASK BIT(5) 263 #define OVRD_SB_RXTERM_EN(x) UPDATE(x, 5, 5) 264 #define SB_RXTERM_EN_MASK BIT(4) 265 #define SB_RXTERM_EN(x) UPDATE(x, 4, 4) 266 #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0) 267 #define ANA_SB_RXTERM_OFFSP(x) UPDATE(x, 3, 0) 268 #define SB_REG0103 0x040C 269 #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3) 270 #define ANA_SB_RXTERM_OFFSN(x) UPDATE(x, 6, 3) 271 #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1) 272 #define OVRD_SB_RX_RESCAL_DONE(x) UPDATE(x, 1, 1) 273 #define SB_RX_RESCAL_DONE_MASK BIT(0) 274 #define SB_RX_RESCAL_DONE(x) UPDATE(x, 0, 0) 275 #define SB_REG0104 0x0410 276 #define OVRD_SB_EN_MASK BIT(5) 277 #define OVRD_SB_EN(x) UPDATE(x, 5, 5) 278 #define SB_EN_MASK BIT(4) 279 #define SB_EN(x) UPDATE(x, 4, 4) 280 #define SB_REG0105 0x0414 281 #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6) 282 #define OVRD_SB_EARC_CMDC_EN(x) UPDATE(x, 6, 6) 283 #define SB_EARC_CMDC_EN_MASK BIT(5) 284 #define SB_EARC_CMDC_EN(x) UPDATE(x, 5, 5) 285 #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0) 286 #define ANA_SB_TX_HLVL_PROG(x) UPDATE(x, 2, 0) 287 #define SB_REG0106 0x0418 288 #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4) 289 #define ANA_SB_TX_LLVL_PROG(x) UPDATE(x, 6, 4) 290 #define SB_REG0107 0x041C 291 #define SB_REG0108 0x0420 292 #define SB_REG0109 0x0424 293 #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0) 294 #define ANA_SB_DMRX_AFC_DIV_RATIO(x) UPDATE(x, 2, 0) 295 #define SB_REG010A 0x0428 296 #define SB_REG010B 0x042C 297 #define SB_REG010C 0x0430 298 #define SB_REG010D 0x0434 299 #define SB_REG010E 0x0438 300 #define SB_REG010F 0x043C 301 #define OVRD_SB_VREG_EN_MASK BIT(7) 302 #define OVRD_SB_VREG_EN(x) UPDATE(x, 7, 7) 303 #define SB_VREG_EN_MASK BIT(6) 304 #define SB_VREG_EN(x) UPDATE(x, 6, 6) 305 #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5) 306 #define OVRD_SB_VREG_LPF_BYPASS(x) UPDATE(x, 5, 5) 307 #define SB_VREG_LPF_BYPASS_MASK BIT(4) 308 #define SB_VREG_LPF_BYPASS(x) UPDATE(x, 4, 4) 309 #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 310 #define ANA_SB_VREG_GAIN_CTRL(x) UPDATE(x, 3, 0) 311 #define SB_REG0110 0x0440 312 #define ANA_SB_VREG_REF_SEL_MASK BIT(0) 313 #define ANA_SB_VREG_REF_SEL(x) UPDATE(x, 0, 0) 314 #define SB_REG0111 0x0444 315 #define SB_REG0112 0x0448 316 #define SB_REG0113 0x044C 317 #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4) 318 #define SB_RX_RCAL_OPT_CODE(x) UPDATE(x, 5, 4) 319 #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0) 320 #define SB_RX_RTERM_CTRL(x) UPDATE(x, 3, 0) 321 #define SB_REG0114 0x0450 322 #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3) 323 #define SB_TG_SB_EN_DELAY_TIME(x) UPDATE(x, 5, 3) 324 #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0) 325 #define SB_TG_RXTERM_EN_DELAY_TIME(x) UPDATE(x, 2, 0) 326 #define SB_REG0115 0x0454 327 #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3) 328 #define SB_READY_DELAY_TIME(x) UPDATE(x, 5, 3) 329 #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0) 330 #define SB_TG_OSC_EN_DELAY_TIME(x) UPDATE(x, 2, 0) 331 #define SB_REG0116 0x0458 332 #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4) 333 #define AFC_RSTN_DELAY_TIME(x) UPDATE(x, 6, 4) 334 #define SB_REG0117 0x045C 335 #define FAST_PULSE_TIME_MASK GENMASK(3, 0) 336 #define FAST_PULSE_TIME(x) UPDATE(x, 3, 0) 337 #define SB_REG0118 0x0460 338 #define SB_REG0119 0x0464 339 #define SB_REG011A 0x0468 340 #define SB_REG011B 0x046C 341 #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4) 342 #define SB_EARC_SIG_DET_BYPASS(x) UPDATE(x, 4, 4) 343 #define SB_AFC_TOL_MASK GENMASK(3, 0) 344 #define SB_AFC_TOL(x) UPDATE(x, 3, 0) 345 #define SB_REG011C 0x0470 346 #define SB_REG011D 0x0474 347 #define SB_REG011E 0x0478 348 #define SB_REG011F 0x047C 349 #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2) 350 #define SB_PWM_AFC_CTRL(x) UPDATE(x, 7, 2) 351 #define SB_RCAL_RSTN_MASK BIT(1) 352 #define SB_RCAL_RSTN(x) UPDATE(x, 1, 1) 353 #define SB_REG0120 0x0480 354 #define SB_EARC_EN_MASK BIT(1) 355 #define SB_EARC_EN(x) UPDATE(x, 1, 1) 356 #define SB_EARC_AFC_EN_MASK BIT(2) 357 #define SB_EARC_AFC_EN(x) UPDATE(x, 2, 2) 358 #define SB_REG0121 0x0484 359 #define SB_REG0122 0x0488 360 #define SB_REG0123 0x048C 361 #define OVRD_SB_READY_MASK BIT(5) 362 #define OVRD_SB_READY(x) UPDATE(x, 5, 5) 363 #define SB_READY_MASK BIT(4) 364 #define SB_READY(x) UPDATE(x, 4, 4) 365 #define SB_REG0124 0x0490 366 #define SB_REG0125 0x0494 367 #define SB_REG0126 0x0498 368 #define SB_REG0127 0x049C 369 #define SB_REG0128 0x04A0 370 #define SB_REG0129 0x04AD 371 #define LNTOP_REG0200 0x0800 372 #define PROTOCOL_SEL BIT(2) 373 #define HDMI_MODE BIT(2) 374 #define HDMI_TMDS_FRL_SEL BIT(1) 375 #define LNTOP_REG0201 0x0804 376 #define LNTOP_REG0202 0x0808 377 #define LNTOP_REG0203 0x080C 378 #define LNTOP_REG0204 0x0810 379 #define LNTOP_REG0205 0x0814 380 #define LNTOP_REG0206 0x0818 381 #define DATA_BUS_WIDTH (0x3 << 1) 382 #define WIDTH_40BIT (0x3 << 1) 383 #define WIDTH_36BIT (0x2 << 1) 384 #define DATA_BUS_SEL BIT(0) 385 #define DATA_BUS_36_40 BIT(0) 386 #define LNTOP_REG0207 0x081C 387 #define LANE_EN 0xf 388 #define ALL_LANE_EN 0xf 389 #define LNTOP_REG0208 0x0820 390 #define LNTOP_REG0209 0x0824 391 #define LNTOP_REG020A 0x0828 392 #define LNTOP_REG020B 0x082C 393 #define LNTOP_REG020C 0x0830 394 #define LNTOP_REG020D 0x0834 395 #define LNTOP_REG020E 0x0838 396 #define LNTOP_REG020F 0x083C 397 #define LNTOP_REG0210 0x0840 398 #define LNTOP_REG0211 0x0844 399 #define LNTOP_REG0212 0x0848 400 #define LNTOP_REG0213 0x084C 401 #define LNTOP_REG0214 0x0850 402 #define LNTOP_REG0215 0x0854 403 #define LNTOP_REG0216 0x0858 404 #define LNTOP_REG0217 0x085C 405 #define LNTOP_REG0218 0x0860 406 #define LNTOP_REG0219 0x0864 407 #define LNTOP_REG021A 0x0868 408 #define LNTOP_REG021B 0x086C 409 #define LNTOP_REG021C 0x0870 410 #define LNTOP_REG021D 0x0874 411 #define LNTOP_REG021E 0x0878 412 #define LNTOP_REG021F 0x087C 413 #define LNTOP_REG0220 0x0880 414 #define LNTOP_REG0221 0x0884 415 #define LNTOP_REG0222 0x0888 416 #define LNTOP_REG0223 0x088C 417 #define LNTOP_REG0224 0x0890 418 #define LNTOP_REG0225 0x0894 419 #define LNTOP_REG0226 0x0898 420 #define LNTOP_REG0227 0x089C 421 #define LNTOP_REG0228 0x08A0 422 #define LNTOP_REG0229 0x08A4 423 #define LANE_REG0300 0x0C00 424 #define LANE_REG0301 0x0C04 425 #define LANE_REG0302 0x0C08 426 #define LANE_REG0303 0x0C0C 427 #define LANE_REG0304 0x0C10 428 #define LANE_REG0305 0x0C14 429 #define LANE_REG0306 0x0C18 430 #define LANE_REG0307 0x0C1C 431 #define LANE_REG0308 0x0C20 432 #define LANE_REG0309 0x0C24 433 #define LANE_REG030A 0x0C28 434 #define LANE_REG030B 0x0C2C 435 #define LANE_REG030C 0x0C30 436 #define LANE_REG030D 0x0C34 437 #define LANE_REG030E 0x0C38 438 #define LANE_REG030F 0x0C3C 439 #define LANE_REG0310 0x0C40 440 #define LANE_REG0311 0x0C44 441 #define LANE_REG0312 0x0C48 442 #define LN0_TX_SER_RATE_SEL_RBR BIT(5) 443 #define LN0_TX_SER_RATE_SEL_HBR BIT(4) 444 #define LN0_TX_SER_RATE_SEL_HBR2 BIT(3) 445 #define LN0_TX_SER_RATE_SEL_HBR3 BIT(2) 446 #define LANE_REG0313 0x0C4C 447 #define LANE_REG0314 0x0C50 448 #define LANE_REG0315 0x0C54 449 #define LANE_REG0316 0x0C58 450 #define LANE_REG0317 0x0C5C 451 #define LANE_REG0318 0x0C60 452 #define LANE_REG0319 0x0C64 453 #define LANE_REG031A 0x0C68 454 #define LANE_REG031B 0x0C6C 455 #define LANE_REG031C 0x0C70 456 #define LANE_REG031D 0x0C74 457 #define LANE_REG031E 0x0C78 458 #define LANE_REG031F 0x0C7C 459 #define LANE_REG0320 0x0C80 460 #define LANE_REG0321 0x0C84 461 #define LANE_REG0322 0x0C88 462 #define LANE_REG0323 0x0C8C 463 #define LANE_REG0324 0x0C90 464 #define LANE_REG0325 0x0C94 465 #define LANE_REG0326 0x0C98 466 #define LANE_REG0327 0x0C9C 467 #define LANE_REG0328 0x0CA0 468 #define LANE_REG0329 0x0CA4 469 #define LANE_REG032A 0x0CA8 470 #define LANE_REG032B 0x0CAC 471 #define LANE_REG032C 0x0CB0 472 #define LANE_REG032D 0x0CB4 473 #define LANE_REG0400 0x1000 474 #define LANE_REG0401 0x1004 475 #define LANE_REG0402 0x1008 476 #define LANE_REG0403 0x100C 477 #define LANE_REG0404 0x1010 478 #define LANE_REG0405 0x1014 479 #define LANE_REG0406 0x1018 480 #define LANE_REG0407 0x101C 481 #define LANE_REG0408 0x1020 482 #define LANE_REG0409 0x1024 483 #define LANE_REG040A 0x1028 484 #define LANE_REG040B 0x102C 485 #define LANE_REG040C 0x1030 486 #define LANE_REG040D 0x1034 487 #define LANE_REG040E 0x1038 488 #define LANE_REG040F 0x103C 489 #define LANE_REG0410 0x1040 490 #define LANE_REG0411 0x1044 491 #define LANE_REG0412 0x1048 492 #define LN1_TX_SER_RATE_SEL_RBR BIT(5) 493 #define LN1_TX_SER_RATE_SEL_HBR BIT(4) 494 #define LN1_TX_SER_RATE_SEL_HBR2 BIT(3) 495 #define LN1_TX_SER_RATE_SEL_HBR3 BIT(2) 496 #define LANE_REG0413 0x104C 497 #define LANE_REG0414 0x1050 498 #define LANE_REG0415 0x1054 499 #define LANE_REG0416 0x1058 500 #define LANE_REG0417 0x105C 501 #define LANE_REG0418 0x1060 502 #define LANE_REG0419 0x1064 503 #define LANE_REG041A 0x1068 504 #define LANE_REG041B 0x106C 505 #define LANE_REG041C 0x1070 506 #define LANE_REG041D 0x1074 507 #define LANE_REG041E 0x1078 508 #define LANE_REG041F 0x107C 509 #define LANE_REG0420 0x1080 510 #define LANE_REG0421 0x1084 511 #define LANE_REG0422 0x1088 512 #define LANE_REG0423 0x108C 513 #define LANE_REG0424 0x1090 514 #define LANE_REG0425 0x1094 515 #define LANE_REG0426 0x1098 516 #define LANE_REG0427 0x109C 517 #define LANE_REG0428 0x10A0 518 #define LANE_REG0429 0x10A4 519 #define LANE_REG042A 0x10A8 520 #define LANE_REG042B 0x10AC 521 #define LANE_REG042C 0x10B0 522 #define LANE_REG042D 0x10B4 523 #define LANE_REG0500 0x1400 524 #define LANE_REG0501 0x1404 525 #define LANE_REG0502 0x1408 526 #define LANE_REG0503 0x140C 527 #define LANE_REG0504 0x1410 528 #define LANE_REG0505 0x1414 529 #define LANE_REG0506 0x1418 530 #define LANE_REG0507 0x141C 531 #define LANE_REG0508 0x1420 532 #define LANE_REG0509 0x1424 533 #define LANE_REG050A 0x1428 534 #define LANE_REG050B 0x142C 535 #define LANE_REG050C 0x1430 536 #define LANE_REG050D 0x1434 537 #define LANE_REG050E 0x1438 538 #define LANE_REG050F 0x143C 539 #define LANE_REG0510 0x1440 540 #define LANE_REG0511 0x1444 541 #define LANE_REG0512 0x1448 542 #define LN2_TX_SER_RATE_SEL_RBR BIT(5) 543 #define LN2_TX_SER_RATE_SEL_HBR BIT(4) 544 #define LN2_TX_SER_RATE_SEL_HBR2 BIT(3) 545 #define LN2_TX_SER_RATE_SEL_HBR3 BIT(2) 546 #define LANE_REG0513 0x144C 547 #define LANE_REG0514 0x1450 548 #define LANE_REG0515 0x1454 549 #define LANE_REG0516 0x1458 550 #define LANE_REG0517 0x145C 551 #define LANE_REG0518 0x1460 552 #define LANE_REG0519 0x1464 553 #define LANE_REG051A 0x1468 554 #define LANE_REG051B 0x146C 555 #define LANE_REG051C 0x1470 556 #define LANE_REG051D 0x1474 557 #define LANE_REG051E 0x1478 558 #define LANE_REG051F 0x147C 559 #define LANE_REG0520 0x1480 560 #define LANE_REG0521 0x1484 561 #define LANE_REG0522 0x1488 562 #define LANE_REG0523 0x148C 563 #define LANE_REG0524 0x1490 564 #define LANE_REG0525 0x1494 565 #define LANE_REG0526 0x1498 566 #define LANE_REG0527 0x149C 567 #define LANE_REG0528 0x14A0 568 #define LANE_REG0529 0x14AD 569 #define LANE_REG052A 0x14A8 570 #define LANE_REG052B 0x14AC 571 #define LANE_REG052C 0x14B0 572 #define LANE_REG052D 0x14B4 573 #define LANE_REG0600 0x1800 574 #define LANE_REG0601 0x1804 575 #define LANE_REG0602 0x1808 576 #define LANE_REG0603 0x180C 577 #define LANE_REG0604 0x1810 578 #define LANE_REG0605 0x1814 579 #define LANE_REG0606 0x1818 580 #define LANE_REG0607 0x181C 581 #define LANE_REG0608 0x1820 582 #define LANE_REG0609 0x1824 583 #define LANE_REG060A 0x1828 584 #define LANE_REG060B 0x182C 585 #define LANE_REG060C 0x1830 586 #define LANE_REG060D 0x1834 587 #define LANE_REG060E 0x1838 588 #define LANE_REG060F 0x183C 589 #define LANE_REG0610 0x1840 590 #define LANE_REG0611 0x1844 591 #define LANE_REG0612 0x1848 592 #define LN3_TX_SER_RATE_SEL_RBR BIT(5) 593 #define LN3_TX_SER_RATE_SEL_HBR BIT(4) 594 #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3) 595 #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2) 596 #define LANE_REG0613 0x184C 597 #define LANE_REG0614 0x1850 598 #define LANE_REG0615 0x1854 599 #define LANE_REG0616 0x1858 600 #define LANE_REG0617 0x185C 601 #define LANE_REG0618 0x1860 602 #define LANE_REG0619 0x1864 603 #define LANE_REG061A 0x1868 604 #define LANE_REG061B 0x186C 605 #define LANE_REG061C 0x1870 606 #define LANE_REG061D 0x1874 607 #define LANE_REG061E 0x1878 608 #define LANE_REG061F 0x187C 609 #define LANE_REG0620 0x1880 610 #define LANE_REG0621 0x1884 611 #define LANE_REG0622 0x1888 612 #define LANE_REG0623 0x188C 613 #define LANE_REG0624 0x1890 614 #define LANE_REG0625 0x1894 615 #define LANE_REG0626 0x1898 616 #define LANE_REG0627 0x189C 617 #define LANE_REG0628 0x18A0 618 #define LANE_REG0629 0x18A4 619 #define LANE_REG062A 0x18A8 620 #define LANE_REG062B 0x18AC 621 #define LANE_REG062C 0x18B0 622 #define LANE_REG062D 0x18B4 623 624 #define DATA_RATE_MASK 0xFFFFFFF 625 #define COLOR_DEPTH_MASK BIT(31) 626 #define HDMI_MODE_MASK BIT(30) 627 #define HDMI_EARC_MASK BIT(29) 628 629 struct lcpll_config { 630 u32 bit_rate; 631 u8 lcvco_mode_en; 632 u8 pi_en; 633 u8 clk_en_100m; 634 u8 pms_mdiv; 635 u8 pms_mdiv_afc; 636 u8 pms_pdiv; 637 u8 pms_refdiv; 638 u8 pms_sdiv; 639 u8 pi_cdiv_rstn; 640 u8 pi_cdiv_sel; 641 u8 sdm_en; 642 u8 sdm_rstn; 643 u8 sdc_frac_en; 644 u8 sdc_rstn; 645 u8 sdm_deno; 646 u8 sdm_num_sign; 647 u8 sdm_num; 648 u8 sdc_n; 649 u8 sdc_n2; 650 u8 sdc_num; 651 u8 sdc_deno; 652 u8 sdc_ndiv_rstn; 653 u8 ssc_en; 654 u8 ssc_fm_dev; 655 u8 ssc_fm_freq; 656 u8 ssc_clk_div_sel; 657 u8 cd_tx_ser_rate_sel; 658 }; 659 660 struct ropll_config { 661 u32 bit_rate; 662 u8 pms_mdiv; 663 u8 pms_mdiv_afc; 664 u8 pms_pdiv; 665 u8 pms_refdiv; 666 u8 pms_sdiv; 667 u8 pms_iqdiv_rstn; 668 u8 ref_clk_sel; 669 u8 sdm_en; 670 u8 sdm_rstn; 671 u8 sdc_frac_en; 672 u8 sdc_rstn; 673 u8 sdm_clk_div; 674 u8 sdm_deno; 675 u8 sdm_num_sign; 676 u8 sdm_num; 677 u8 sdc_n; 678 u8 sdc_num; 679 u8 sdc_deno; 680 u8 sdc_ndiv_rstn; 681 u8 ssc_en; 682 u8 ssc_fm_dev; 683 u8 ssc_fm_freq; 684 u8 ssc_clk_div_sel; 685 u8 ana_cpp_ctrl; 686 u8 ana_lpf_c_sel; 687 u8 cd_tx_ser_rate_sel; 688 }; 689 690 struct rockchip_hdptx_phy { 691 struct udevice *dev; 692 void __iomem *base; 693 struct regmap *grf; 694 695 int id; 696 bool dclk_en; 697 bool pll_locked; 698 699 unsigned long rate; 700 u32 bus_width; 701 702 struct reset_ctl apb_reset; 703 struct reset_ctl cmn_reset; 704 struct reset_ctl init_reset; 705 struct reset_ctl lane_reset; 706 struct reset_ctl phy_reset; 707 struct reset_ctl ropll_reset; 708 struct reset_ctl lcpll_reset; 709 }; 710 711 struct clk_hdptx { 712 struct udevice *dev; 713 ulong rate; 714 }; 715 716 /* global variables are used to pass reource from phy drivers to clk driver */ 717 static struct rockchip_hdptx_phy *g_hdptx0; 718 static struct rockchip_hdptx_phy *g_hdptx1; 719 720 struct lcpll_config lcpll_cfg[] = { 721 { 48000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2, 722 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, 723 }, 724 { 40000000, 1, 1, 0, 0x68, 0x68, 1, 1, 0, 0, 0, 1, 1, 1, 1, 9, 0, 1, 1, 725 0, 2, 3, 1, 0, 0x20, 0x0c, 1, 0, 726 }, 727 { 32000000, 1, 1, 1, 0x6b, 0x6b, 1, 1, 0, 1, 2, 1, 1, 1, 1, 9, 1, 2, 1, 728 0, 0x0d, 0x18, 1, 0, 0x20, 0x0c, 1, 1, 729 }, 730 { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 731 0, 0, 0, 0, 0, 0, 732 }, 733 }; 734 735 struct ropll_config ropll_frl_cfg[] = { 736 { 24000000, 0x19, 0x19, 1, 1, 0, 1, 2, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 737 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 738 }, 739 { 18000000, 0x7d, 0x7d, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 740 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 741 }, 742 { 9000000, 0x7d, 0x7d, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 743 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 744 }, 745 { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 746 0, 0, 0, 0, 747 }, 748 }; 749 750 struct ropll_config ropll_tmds_cfg[] = { 751 { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 752 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 753 }, 754 { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 755 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 756 }, 757 { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 758 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 759 }, 760 { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 761 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 762 }, 763 { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 764 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 765 }, 766 { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 767 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 768 }, 769 { 1462500, 122, 122, 1, 1, 4, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 1, 0, 1, 770 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 771 }, 772 { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, 773 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 774 }, 775 { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 776 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 777 }, 778 { 855000, 125, 125, 1, 1, 6, 1, 1, 1, 1, 1, 1, 1, 80, 1, 16, 2, 0, 779 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 780 }, 781 { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, 782 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 783 }, 784 { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 785 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 786 }, 787 { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 788 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 789 }, 790 { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, 791 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 792 }, 793 { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 1, 794 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 795 }, 796 { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 797 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 798 }, 799 { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 800 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 801 }, 802 { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 803 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, 804 }, 805 { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 806 0, 0, 0, 0, 807 }, 808 }; 809 810 static inline void hdptx_write(struct rockchip_hdptx_phy *hdptx, uint reg, 811 uint val) 812 { 813 writel(val, hdptx->base + reg); 814 } 815 816 static inline uint hdptx_read(struct rockchip_hdptx_phy *hdptx, uint reg) 817 { 818 return readl(hdptx->base + reg); 819 } 820 821 static void hdptx_update_bits(struct rockchip_hdptx_phy *hdptx, uint reg, 822 uint mask, uint val) 823 { 824 uint orig, tmp; 825 826 orig = hdptx_read(hdptx, reg); 827 tmp = orig & ~mask; 828 tmp |= val & mask; 829 hdptx_write(hdptx, reg, tmp); 830 } 831 832 static void hdptx_grf_write(struct rockchip_hdptx_phy *hdptx, uint reg, 833 uint val) 834 { 835 regmap_write(hdptx->grf, reg, val); 836 } 837 838 static uint hdptx_grf_read(struct rockchip_hdptx_phy *hdptx, uint reg) 839 { 840 uint val; 841 int ret; 842 843 ret = regmap_read(hdptx->grf, reg, &val); 844 if (ret) 845 dev_err(hdptx->dev, "regmap_read err:%d", ret); 846 847 return val; 848 } 849 850 static void hdptx_pre_power_up(struct rockchip_hdptx_phy *hdptx) 851 { 852 u32 val = 0; 853 854 reset_assert(&hdptx->apb_reset); 855 udelay(20); 856 reset_deassert(&hdptx->apb_reset); 857 858 reset_assert(&hdptx->lane_reset); 859 reset_assert(&hdptx->cmn_reset); 860 reset_assert(&hdptx->init_reset); 861 862 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; 863 hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val); 864 } 865 866 static int hdptx_post_enable_lane(struct rockchip_hdptx_phy *hdptx) 867 { 868 u32 val = 0; 869 int i; 870 871 reset_deassert(&hdptx->lane_reset); 872 873 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | HDPTX_I_BIAS_EN | 874 HDPTX_I_BGR_EN; 875 hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val); 876 877 val = 0; 878 for (i = 0; i < 20; i++) { 879 val = hdptx_grf_read(hdptx, GRF_HDPTX_STATUS); 880 881 if (val & HDPTX_O_PHY_RDY && val & HDPTX_O_PLL_LOCK_DONE) 882 break; 883 udelay(100); 884 } 885 886 if (i == 20) { 887 dev_err(hdptx->dev, "hdptx phy lane can't ready!\n"); 888 return -EINVAL; 889 } 890 891 dev_err(hdptx->dev, "hdptx phy lane locked!\n"); 892 893 return 0; 894 } 895 896 static int hdptx_post_enable_pll(struct rockchip_hdptx_phy *hdptx) 897 { 898 u32 val = 0; 899 int i; 900 901 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | HDPTX_I_BIAS_EN | 902 HDPTX_I_BGR_EN; 903 hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val); 904 udelay(10); 905 reset_deassert(&hdptx->init_reset); 906 udelay(10); 907 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; 908 hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val); 909 udelay(10); 910 reset_deassert(&hdptx->cmn_reset); 911 912 val = 0; 913 for (i = 0; i < 20; i++) { 914 val = hdptx_grf_read(hdptx, GRF_HDPTX_STATUS); 915 916 if (val & HDPTX_O_PHY_CLK_RDY) 917 break; 918 udelay(20); 919 } 920 921 if (i == 20) { 922 dev_err(hdptx->dev, "hdptx phy pll can't lock!\n"); 923 return -EINVAL; 924 } 925 926 hdptx->pll_locked = true; 927 dev_err(hdptx->dev, "hdptx phy pll locked!\n"); 928 929 return 0; 930 } 931 932 static int hdptx_post_power_up(struct rockchip_hdptx_phy *hdptx) 933 { 934 u32 val = 0; 935 int i; 936 937 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | HDPTX_I_BIAS_EN | 938 HDPTX_I_BGR_EN; 939 hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val); 940 udelay(10); 941 reset_deassert(&hdptx->init_reset); 942 udelay(10); 943 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; 944 hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val); 945 udelay(10); 946 reset_deassert(&hdptx->cmn_reset); 947 948 for (i = 0; i < 20; i++) { 949 val = hdptx_grf_read(hdptx, GRF_HDPTX_STATUS); 950 951 if (val & HDPTX_O_PLL_LOCK_DONE) 952 break; 953 udelay(20); 954 } 955 956 if (i == 20) { 957 dev_err(hdptx->dev, "hdptx phy can't lock!\n"); 958 return -EINVAL; 959 } 960 961 udelay(20); 962 963 reset_deassert(&hdptx->lane_reset); 964 965 for (i = 0; i < 20; i++) { 966 val = hdptx_grf_read(hdptx, GRF_HDPTX_STATUS); 967 968 if (val & HDPTX_O_PHY_RDY) 969 break; 970 udelay(100); 971 } 972 973 if (i == 20) { 974 dev_err(hdptx->dev, "hdptx phy can't ready!\n"); 975 return -EINVAL; 976 } 977 978 dev_err(hdptx->dev, "hdptx phy locked!\n"); 979 980 return 0; 981 } 982 983 static bool hdptx_phy_clk_pll_calc(unsigned int data_rate, 984 struct ropll_config *cfg) 985 { 986 unsigned int fref = 24000; 987 unsigned int sdc; 988 unsigned int fout = data_rate / 2; 989 unsigned int fvco; 990 u32 mdiv, sdiv, n = 8; 991 unsigned long k = 0, lc, k_sub, lc_sub; 992 993 for (sdiv = 1; sdiv <= 16; sdiv++) { 994 if (sdiv % 2 && sdiv != 1) 995 continue; 996 997 fvco = fout * sdiv; 998 999 if (fvco < 2000000 || fvco > 4000000) 1000 continue; 1001 1002 mdiv = DIV_ROUND_UP(fvco, fref); 1003 if (mdiv < 20 || mdiv > 255) 1004 continue; 1005 1006 if (fref * mdiv - fvco) { 1007 for (sdc = 264000; sdc <= 750000; sdc += fref) 1008 if (sdc * n > fref * mdiv) 1009 break; 1010 1011 if (sdc > 750000) 1012 continue; 1013 1014 rational_best_approximation(fref * mdiv - fvco, 1015 sdc / 16, 1016 GENMASK(6, 0), 1017 GENMASK(7, 0), 1018 &k, &lc); 1019 1020 rational_best_approximation(sdc * n - fref * mdiv, 1021 sdc, 1022 GENMASK(6, 0), 1023 GENMASK(7, 0), 1024 &k_sub, &lc_sub); 1025 } 1026 1027 break; 1028 } 1029 1030 if (sdiv > 16) 1031 return false; 1032 1033 if (cfg) { 1034 cfg->pms_mdiv = mdiv; 1035 cfg->pms_mdiv_afc = mdiv; 1036 cfg->pms_pdiv = 1; 1037 cfg->pms_refdiv = 1; 1038 cfg->pms_sdiv = sdiv - 1; 1039 1040 cfg->sdm_en = k > 0 ? 1 : 0; 1041 if (cfg->sdm_en) { 1042 cfg->sdm_deno = lc; 1043 cfg->sdm_num_sign = 1; 1044 cfg->sdm_num = k; 1045 cfg->sdc_n = n - 3; 1046 cfg->sdc_num = k_sub; 1047 cfg->sdc_deno = lc_sub; 1048 } 1049 } 1050 1051 return true; 1052 } 1053 1054 static int hdptx_ropll_cmn_config(struct rockchip_hdptx_phy *hdptx, unsigned long bit_rate) 1055 { 1056 int bus_width = hdptx->bus_width; 1057 u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; 1058 struct ropll_config *cfg = ropll_tmds_cfg; 1059 struct ropll_config rc = {0}; 1060 1061 printf("%s bus_width:%x rate:%lu\n", __func__, bus_width, bit_rate); 1062 hdptx->rate = bit_rate * 100; 1063 1064 for (; cfg->bit_rate != ~0; cfg++) 1065 if (bit_rate == cfg->bit_rate) 1066 break; 1067 1068 if (cfg->bit_rate == ~0) { 1069 if (hdptx_phy_clk_pll_calc(bit_rate, &rc)) { 1070 cfg = &rc; 1071 } else { 1072 dev_err(hdptx->dev, "%s can't find pll cfg\n", __func__); 1073 return -EINVAL; 1074 } 1075 } 1076 1077 dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u\n", 1078 cfg->pms_mdiv, cfg->pms_sdiv + 1); 1079 dev_dbg(hdptx->dev, "sdm_en=%u, k_sign=%u, k=%u, lc=%u", 1080 cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); 1081 dev_dbg(hdptx->dev, "n=%u, k_sub=%u, lc_sub=%u\n", 1082 cfg->sdc_n + 3, cfg->sdc_num, cfg->sdc_deno); 1083 1084 hdptx_pre_power_up(hdptx); 1085 1086 reset_assert(&hdptx->ropll_reset); 1087 udelay(20); 1088 reset_deassert(&hdptx->ropll_reset); 1089 1090 hdptx_write(hdptx, CMN_REG0008, 0x00); 1091 hdptx_write(hdptx, CMN_REG0009, 0x0c); 1092 hdptx_write(hdptx, CMN_REG000A, 0x83); 1093 hdptx_write(hdptx, CMN_REG000B, 0x06); 1094 hdptx_write(hdptx, CMN_REG000C, 0x20); 1095 hdptx_write(hdptx, CMN_REG000D, 0xb8); 1096 hdptx_write(hdptx, CMN_REG000E, 0x0f); 1097 hdptx_write(hdptx, CMN_REG000F, 0x0f); 1098 hdptx_write(hdptx, CMN_REG0010, 0x04); 1099 hdptx_write(hdptx, CMN_REG0011, 0x01); 1100 hdptx_write(hdptx, CMN_REG0012, 0x26); 1101 hdptx_write(hdptx, CMN_REG0013, 0x22); 1102 hdptx_write(hdptx, CMN_REG0014, 0x24); 1103 hdptx_write(hdptx, CMN_REG0015, 0x77); 1104 hdptx_write(hdptx, CMN_REG0016, 0x08); 1105 hdptx_write(hdptx, CMN_REG0017, 0x20); 1106 hdptx_write(hdptx, CMN_REG0018, 0x04); 1107 hdptx_write(hdptx, CMN_REG0019, 0x48); 1108 hdptx_write(hdptx, CMN_REG001A, 0x01); 1109 hdptx_write(hdptx, CMN_REG001B, 0x00); 1110 hdptx_write(hdptx, CMN_REG001C, 0x01); 1111 hdptx_write(hdptx, CMN_REG001D, 0x64); 1112 hdptx_write(hdptx, CMN_REG001E, 0x14); 1113 hdptx_write(hdptx, CMN_REG001F, 0x00); 1114 hdptx_write(hdptx, CMN_REG0020, 0x00); 1115 hdptx_write(hdptx, CMN_REG0021, 0x00); 1116 hdptx_write(hdptx, CMN_REG0022, 0x11); 1117 hdptx_write(hdptx, CMN_REG0023, 0x00); 1118 hdptx_write(hdptx, CMN_REG0024, 0x00); 1119 hdptx_write(hdptx, CMN_REG0025, 0x53); 1120 hdptx_write(hdptx, CMN_REG0026, 0x00); 1121 hdptx_write(hdptx, CMN_REG0027, 0x00); 1122 hdptx_write(hdptx, CMN_REG0028, 0x01); 1123 hdptx_write(hdptx, CMN_REG0029, 0x01); 1124 hdptx_write(hdptx, CMN_REG002A, 0x00); 1125 hdptx_write(hdptx, CMN_REG002B, 0x00); 1126 hdptx_write(hdptx, CMN_REG002C, 0x00); 1127 hdptx_write(hdptx, CMN_REG002D, 0x00); 1128 hdptx_write(hdptx, CMN_REG002E, 0x04); 1129 hdptx_write(hdptx, CMN_REG002F, 0x00); 1130 hdptx_write(hdptx, CMN_REG0030, 0x20); 1131 hdptx_write(hdptx, CMN_REG0031, 0x30); 1132 hdptx_write(hdptx, CMN_REG0032, 0x0b); 1133 hdptx_write(hdptx, CMN_REG0033, 0x23); 1134 hdptx_write(hdptx, CMN_REG0034, 0x00); 1135 hdptx_write(hdptx, CMN_REG0035, 0x00); 1136 hdptx_write(hdptx, CMN_REG0038, 0x00); 1137 hdptx_write(hdptx, CMN_REG0039, 0x00); 1138 hdptx_write(hdptx, CMN_REG003A, 0x00); 1139 hdptx_write(hdptx, CMN_REG003B, 0x00); 1140 hdptx_write(hdptx, CMN_REG003C, 0x80); 1141 hdptx_write(hdptx, CMN_REG003D, 0x40); 1142 hdptx_write(hdptx, CMN_REG003E, 0x0c); 1143 hdptx_write(hdptx, CMN_REG003F, 0x83); 1144 hdptx_write(hdptx, CMN_REG0040, 0x06); 1145 hdptx_write(hdptx, CMN_REG0041, 0x20); 1146 hdptx_write(hdptx, CMN_REG0042, 0x78); 1147 hdptx_write(hdptx, CMN_REG0043, 0x00); 1148 hdptx_write(hdptx, CMN_REG0044, 0x46); 1149 hdptx_write(hdptx, CMN_REG0045, 0x24); 1150 hdptx_write(hdptx, CMN_REG0046, 0xff); 1151 hdptx_write(hdptx, CMN_REG0047, 0x00); 1152 hdptx_write(hdptx, CMN_REG0048, 0x44); 1153 hdptx_write(hdptx, CMN_REG0049, 0xfa); 1154 hdptx_write(hdptx, CMN_REG004A, 0x08); 1155 hdptx_write(hdptx, CMN_REG004B, 0x00); 1156 hdptx_write(hdptx, CMN_REG004C, 0x01); 1157 hdptx_write(hdptx, CMN_REG004D, 0x64); 1158 hdptx_write(hdptx, CMN_REG004E, 0x34); 1159 hdptx_write(hdptx, CMN_REG004F, 0x00); 1160 hdptx_write(hdptx, CMN_REG0050, 0x00); 1161 1162 hdptx_write(hdptx, CMN_REG0051, cfg->pms_mdiv); 1163 hdptx_write(hdptx, CMN_REG0055, cfg->pms_mdiv_afc); 1164 1165 hdptx_write(hdptx, CMN_REG0059, (cfg->pms_pdiv << 4) | cfg->pms_refdiv); 1166 1167 hdptx_write(hdptx, CMN_REG005A, (cfg->pms_sdiv << 4)); 1168 1169 hdptx_write(hdptx, CMN_REG005C, 0x25); 1170 hdptx_write(hdptx, CMN_REG005D, 0x0c); 1171 hdptx_write(hdptx, CMN_REG005E, 0x4f); 1172 hdptx_update_bits(hdptx, CMN_REG005E, ROPLL_SDM_EN_MASK, 1173 ROPLL_SDM_EN(cfg->sdm_en)); 1174 if (!cfg->sdm_en) 1175 hdptx_update_bits(hdptx, CMN_REG005E, 0xf, 0); 1176 1177 hdptx_write(hdptx, CMN_REG005F, 0x01); 1178 1179 hdptx_update_bits(hdptx, CMN_REG0064, ROPLL_SDM_NUM_SIGN_RBR_MASK, 1180 ROPLL_SDM_NUM_SIGN_RBR(cfg->sdm_num_sign)); 1181 hdptx_write(hdptx, CMN_REG0065, cfg->sdm_num); 1182 hdptx_write(hdptx, CMN_REG0060, cfg->sdm_deno); 1183 1184 hdptx_update_bits(hdptx, CMN_REG0069, ROPLL_SDC_N_RBR_MASK, 1185 ROPLL_SDC_N_RBR(cfg->sdc_n)); 1186 1187 hdptx_write(hdptx, CMN_REG006C, cfg->sdc_num); 1188 hdptx_write(hdptx, CMN_REG0070, cfg->sdc_deno); 1189 1190 hdptx_write(hdptx, CMN_REG006B, 0x04); 1191 1192 hdptx_write(hdptx, CMN_REG0073, 0x30); 1193 hdptx_write(hdptx, CMN_REG0074, 0x04); 1194 hdptx_write(hdptx, CMN_REG0075, 0x20); 1195 hdptx_write(hdptx, CMN_REG0076, 0x30); 1196 hdptx_write(hdptx, CMN_REG0077, 0x08); 1197 hdptx_write(hdptx, CMN_REG0078, 0x0c); 1198 hdptx_write(hdptx, CMN_REG0079, 0x00); 1199 hdptx_write(hdptx, CMN_REG007B, 0x00); 1200 hdptx_write(hdptx, CMN_REG007C, 0x00); 1201 hdptx_write(hdptx, CMN_REG007D, 0x00); 1202 hdptx_write(hdptx, CMN_REG007E, 0x00); 1203 hdptx_write(hdptx, CMN_REG007F, 0x00); 1204 hdptx_write(hdptx, CMN_REG0080, 0x00); 1205 hdptx_write(hdptx, CMN_REG0081, 0x01); 1206 hdptx_write(hdptx, CMN_REG0082, 0x04); 1207 hdptx_write(hdptx, CMN_REG0083, 0x24); 1208 hdptx_write(hdptx, CMN_REG0084, 0x20); 1209 hdptx_write(hdptx, CMN_REG0085, 0x03); 1210 1211 hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_POSTDIV_SEL_MASK, 1212 PLL_PCG_POSTDIV_SEL(cfg->pms_sdiv)); 1213 1214 hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_CLK_SEL_MASK, 1215 PLL_PCG_CLK_SEL(color_depth)); 1216 1217 hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_CLK_EN, PLL_PCG_CLK_EN); 1218 1219 hdptx_write(hdptx, CMN_REG0087, 0x04); 1220 hdptx_write(hdptx, CMN_REG0089, 0x00); 1221 hdptx_write(hdptx, CMN_REG008A, 0x55); 1222 hdptx_write(hdptx, CMN_REG008B, 0x25); 1223 hdptx_write(hdptx, CMN_REG008C, 0x2c); 1224 hdptx_write(hdptx, CMN_REG008D, 0x22); 1225 hdptx_write(hdptx, CMN_REG008E, 0x14); 1226 hdptx_write(hdptx, CMN_REG008F, 0x20); 1227 hdptx_write(hdptx, CMN_REG0090, 0x00); 1228 hdptx_write(hdptx, CMN_REG0091, 0x00); 1229 hdptx_write(hdptx, CMN_REG0092, 0x00); 1230 hdptx_write(hdptx, CMN_REG0093, 0x00); 1231 hdptx_write(hdptx, CMN_REG0095, 0x00); 1232 hdptx_write(hdptx, CMN_REG0097, 0x02); 1233 hdptx_write(hdptx, CMN_REG0099, 0x04); 1234 hdptx_write(hdptx, CMN_REG009A, 0x11); 1235 hdptx_write(hdptx, CMN_REG009B, 0x00); 1236 1237 return hdptx_post_enable_pll(hdptx); 1238 } 1239 1240 static int hdptx_ropll_tmds_mode_config(struct rockchip_hdptx_phy *hdptx, u32 rate) 1241 { 1242 u32 bit_rate = rate & DATA_RATE_MASK; 1243 u8 color_depth = (rate & COLOR_DEPTH_MASK) ? 1 : 0; 1244 1245 if (color_depth) 1246 bit_rate = bit_rate * 5 / 4; 1247 1248 if (!hdptx->pll_locked) { 1249 int ret; 1250 1251 ret = hdptx_ropll_cmn_config(hdptx, bit_rate); 1252 if (ret) 1253 return ret; 1254 } 1255 1256 hdptx_write(hdptx, SB_REG0114, 0x00); 1257 hdptx_write(hdptx, SB_REG0115, 0x00); 1258 hdptx_write(hdptx, SB_REG0116, 0x00); 1259 hdptx_write(hdptx, SB_REG0117, 0x00); 1260 hdptx_write(hdptx, LNTOP_REG0200, 0x06); 1261 1262 if (bit_rate >= 3400000) { 1263 /* For 1/40 bitrate clk */ 1264 hdptx_write(hdptx, LNTOP_REG0201, 0x00); 1265 hdptx_write(hdptx, LNTOP_REG0202, 0x00); 1266 hdptx_write(hdptx, LNTOP_REG0203, 0x0f); 1267 hdptx_write(hdptx, LNTOP_REG0204, 0xff); 1268 hdptx_write(hdptx, LNTOP_REG0205, 0xff); 1269 } else { 1270 /* For 1/10 bitrate clk */ 1271 hdptx_write(hdptx, LNTOP_REG0201, 0x07); 1272 hdptx_write(hdptx, LNTOP_REG0202, 0xc1); 1273 hdptx_write(hdptx, LNTOP_REG0203, 0xf0); 1274 hdptx_write(hdptx, LNTOP_REG0204, 0x7c); 1275 hdptx_write(hdptx, LNTOP_REG0205, 0x1f); 1276 } 1277 1278 hdptx_write(hdptx, LNTOP_REG0206, 0x07); 1279 hdptx_write(hdptx, LNTOP_REG0207, 0x0f); 1280 hdptx_write(hdptx, LANE_REG0303, 0x0c); 1281 hdptx_write(hdptx, LANE_REG0307, 0x20); 1282 hdptx_write(hdptx, LANE_REG030A, 0x17); 1283 hdptx_write(hdptx, LANE_REG030B, 0x77); 1284 hdptx_write(hdptx, LANE_REG030C, 0x77); 1285 hdptx_write(hdptx, LANE_REG030D, 0x77); 1286 hdptx_write(hdptx, LANE_REG030E, 0x38); 1287 hdptx_write(hdptx, LANE_REG0310, 0x03); 1288 hdptx_write(hdptx, LANE_REG0311, 0x0f); 1289 hdptx_write(hdptx, LANE_REG0312, 0x00); 1290 hdptx_write(hdptx, LANE_REG0316, 0x02); 1291 hdptx_write(hdptx, LANE_REG031B, 0x01); 1292 hdptx_write(hdptx, LANE_REG031E, 0x00); 1293 hdptx_write(hdptx, LANE_REG031F, 0x15); 1294 hdptx_write(hdptx, LANE_REG0320, 0xa0); 1295 hdptx_write(hdptx, LANE_REG0403, 0x0c); 1296 hdptx_write(hdptx, LANE_REG0407, 0x20); 1297 hdptx_write(hdptx, LANE_REG040A, 0x17); 1298 hdptx_write(hdptx, LANE_REG040B, 0x77); 1299 hdptx_write(hdptx, LANE_REG040C, 0x77); 1300 hdptx_write(hdptx, LANE_REG040D, 0x77); 1301 hdptx_write(hdptx, LANE_REG040E, 0x38); 1302 hdptx_write(hdptx, LANE_REG0410, 0x03); 1303 hdptx_write(hdptx, LANE_REG0411, 0x0f); 1304 hdptx_write(hdptx, LANE_REG0412, 0x00); 1305 hdptx_write(hdptx, LANE_REG0416, 0x02); 1306 hdptx_write(hdptx, LANE_REG041B, 0x01); 1307 hdptx_write(hdptx, LANE_REG041E, 0x00); 1308 hdptx_write(hdptx, LANE_REG041F, 0x15); 1309 hdptx_write(hdptx, LANE_REG0420, 0xa0); 1310 hdptx_write(hdptx, LANE_REG0503, 0x0c); 1311 hdptx_write(hdptx, LANE_REG0507, 0x20); 1312 hdptx_write(hdptx, LANE_REG050A, 0x17); 1313 hdptx_write(hdptx, LANE_REG050B, 0x77); 1314 hdptx_write(hdptx, LANE_REG050C, 0x77); 1315 hdptx_write(hdptx, LANE_REG050D, 0x77); 1316 hdptx_write(hdptx, LANE_REG050E, 0x38); 1317 hdptx_write(hdptx, LANE_REG0510, 0x03); 1318 hdptx_write(hdptx, LANE_REG0511, 0x0f); 1319 hdptx_write(hdptx, LANE_REG0512, 0x00); 1320 hdptx_write(hdptx, LANE_REG0516, 0x02); 1321 hdptx_write(hdptx, LANE_REG051B, 0x01); 1322 hdptx_write(hdptx, LANE_REG051E, 0x00); 1323 hdptx_write(hdptx, LANE_REG051F, 0x15); 1324 hdptx_write(hdptx, LANE_REG0520, 0xa0); 1325 hdptx_write(hdptx, LANE_REG0603, 0x0c); 1326 hdptx_write(hdptx, LANE_REG0607, 0x20); 1327 hdptx_write(hdptx, LANE_REG060A, 0x17); 1328 hdptx_write(hdptx, LANE_REG060B, 0x77); 1329 hdptx_write(hdptx, LANE_REG060C, 0x77); 1330 hdptx_write(hdptx, LANE_REG060D, 0x77); 1331 hdptx_write(hdptx, LANE_REG060E, 0x38); 1332 hdptx_write(hdptx, LANE_REG0610, 0x03); 1333 hdptx_write(hdptx, LANE_REG0611, 0x0f); 1334 hdptx_write(hdptx, LANE_REG0612, 0x00); 1335 hdptx_write(hdptx, LANE_REG0616, 0x02); 1336 hdptx_write(hdptx, LANE_REG061B, 0x01); 1337 hdptx_write(hdptx, LANE_REG061E, 0x08); 1338 hdptx_write(hdptx, LANE_REG061F, 0x15); 1339 hdptx_write(hdptx, LANE_REG0620, 0xa0); 1340 1341 hdptx_write(hdptx, LANE_REG0303, 0x2f); 1342 hdptx_write(hdptx, LANE_REG0403, 0x2f); 1343 hdptx_write(hdptx, LANE_REG0503, 0x2f); 1344 hdptx_write(hdptx, LANE_REG0603, 0x2f); 1345 hdptx_write(hdptx, LANE_REG0305, 0x03); 1346 hdptx_write(hdptx, LANE_REG0405, 0x03); 1347 hdptx_write(hdptx, LANE_REG0505, 0x03); 1348 hdptx_write(hdptx, LANE_REG0605, 0x03); 1349 hdptx_write(hdptx, LANE_REG0306, 0x1c); 1350 hdptx_write(hdptx, LANE_REG0406, 0x1c); 1351 hdptx_write(hdptx, LANE_REG0506, 0x1c); 1352 hdptx_write(hdptx, LANE_REG0606, 0x1c); 1353 1354 return hdptx_post_enable_lane(hdptx); 1355 } 1356 1357 static int hdptx_ropll_frl_mode_config(struct rockchip_hdptx_phy *hdptx, u32 rate) 1358 { 1359 u32 bit_rate = rate & DATA_RATE_MASK; 1360 u8 color_depth = (rate & COLOR_DEPTH_MASK) ? 1 : 0; 1361 struct ropll_config *cfg = ropll_frl_cfg; 1362 1363 for (; cfg->bit_rate != ~0; cfg++) 1364 if (bit_rate == cfg->bit_rate) 1365 break; 1366 1367 if (cfg->bit_rate == ~0) { 1368 dev_err(hdptx->dev, "%s can't find pll cfg\n", __func__); 1369 return -EINVAL; 1370 } 1371 1372 hdptx_pre_power_up(hdptx); 1373 1374 reset_assert(&hdptx->ropll_reset); 1375 udelay(20); 1376 reset_deassert(&hdptx->ropll_reset); 1377 1378 hdptx_write(hdptx, CMN_REG0008, 0x00); 1379 hdptx_write(hdptx, CMN_REG0009, 0x0c); 1380 hdptx_write(hdptx, CMN_REG000A, 0x83); 1381 hdptx_write(hdptx, CMN_REG000B, 0x06); 1382 hdptx_write(hdptx, CMN_REG000C, 0x20); 1383 hdptx_write(hdptx, CMN_REG000D, 0xb8); 1384 hdptx_write(hdptx, CMN_REG000E, 0x0f); 1385 hdptx_write(hdptx, CMN_REG000F, 0x0f); 1386 hdptx_write(hdptx, CMN_REG0010, 0x04); 1387 hdptx_write(hdptx, CMN_REG0011, 0x00); 1388 hdptx_write(hdptx, CMN_REG0012, 0x26); 1389 hdptx_write(hdptx, CMN_REG0013, 0x22); 1390 hdptx_write(hdptx, CMN_REG0014, 0x24); 1391 hdptx_write(hdptx, CMN_REG0015, 0x77); 1392 hdptx_write(hdptx, CMN_REG0016, 0x08); 1393 hdptx_write(hdptx, CMN_REG0017, 0x00); 1394 hdptx_write(hdptx, CMN_REG0018, 0x04); 1395 hdptx_write(hdptx, CMN_REG0019, 0x48); 1396 hdptx_write(hdptx, CMN_REG001A, 0x01); 1397 hdptx_write(hdptx, CMN_REG001B, 0x00); 1398 hdptx_write(hdptx, CMN_REG001C, 0x01); 1399 hdptx_write(hdptx, CMN_REG001D, 0x64); 1400 hdptx_write(hdptx, CMN_REG001E, 0x14); 1401 hdptx_write(hdptx, CMN_REG001F, 0x00); 1402 hdptx_write(hdptx, CMN_REG0020, 0x00); 1403 hdptx_write(hdptx, CMN_REG0021, 0x00); 1404 hdptx_write(hdptx, CMN_REG0022, 0x11); 1405 hdptx_write(hdptx, CMN_REG0023, 0x00); 1406 hdptx_write(hdptx, CMN_REG0025, 0x00); 1407 hdptx_write(hdptx, CMN_REG0026, 0x53); 1408 hdptx_write(hdptx, CMN_REG0027, 0x00); 1409 hdptx_write(hdptx, CMN_REG0028, 0x00); 1410 hdptx_write(hdptx, CMN_REG0029, 0x01); 1411 hdptx_write(hdptx, CMN_REG002A, 0x01); 1412 hdptx_write(hdptx, CMN_REG002B, 0x00); 1413 hdptx_write(hdptx, CMN_REG002C, 0x00); 1414 hdptx_write(hdptx, CMN_REG002D, 0x00); 1415 hdptx_write(hdptx, CMN_REG002E, 0x00); 1416 hdptx_write(hdptx, CMN_REG002F, 0x04); 1417 hdptx_write(hdptx, CMN_REG0030, 0x00); 1418 hdptx_write(hdptx, CMN_REG0031, 0x20); 1419 hdptx_write(hdptx, CMN_REG0032, 0x30); 1420 hdptx_write(hdptx, CMN_REG0033, 0x0b); 1421 hdptx_write(hdptx, CMN_REG0034, 0x23); 1422 hdptx_write(hdptx, CMN_REG0035, 0x00); 1423 hdptx_write(hdptx, CMN_REG0038, 0x00); 1424 hdptx_write(hdptx, CMN_REG0039, 0x00); 1425 hdptx_write(hdptx, CMN_REG003A, 0x00); 1426 hdptx_write(hdptx, CMN_REG003B, 0x00); 1427 hdptx_write(hdptx, CMN_REG003C, 0x80); 1428 hdptx_write(hdptx, CMN_REG003D, 0x40); 1429 hdptx_write(hdptx, CMN_REG003E, 0x0c); 1430 hdptx_write(hdptx, CMN_REG003F, 0x83); 1431 hdptx_write(hdptx, CMN_REG0040, 0x06); 1432 hdptx_write(hdptx, CMN_REG0041, 0x20); 1433 hdptx_write(hdptx, CMN_REG0042, 0xb8); 1434 hdptx_write(hdptx, CMN_REG0043, 0x00); 1435 hdptx_write(hdptx, CMN_REG0044, 0x46); 1436 hdptx_write(hdptx, CMN_REG0045, 0x24); 1437 hdptx_write(hdptx, CMN_REG0046, 0xff); 1438 hdptx_write(hdptx, CMN_REG0047, 0x00); 1439 hdptx_write(hdptx, CMN_REG0048, 0x44); 1440 hdptx_write(hdptx, CMN_REG0049, 0xfa); 1441 hdptx_write(hdptx, CMN_REG004A, 0x08); 1442 hdptx_write(hdptx, CMN_REG004B, 0x00); 1443 hdptx_write(hdptx, CMN_REG004C, 0x01); 1444 hdptx_write(hdptx, CMN_REG004D, 0x64); 1445 hdptx_write(hdptx, CMN_REG004E, 0x14); 1446 hdptx_write(hdptx, CMN_REG004F, 0x00); 1447 hdptx_write(hdptx, CMN_REG0050, 0x00); 1448 hdptx_write(hdptx, CMN_REG0051, cfg->pms_mdiv); 1449 hdptx_write(hdptx, CMN_REG0055, cfg->pms_mdiv_afc); 1450 hdptx_write(hdptx, CMN_REG0059, (cfg->pms_pdiv << 4) | cfg->pms_refdiv); 1451 hdptx_write(hdptx, CMN_REG005A, (cfg->pms_sdiv << 4)); 1452 hdptx_write(hdptx, CMN_REG005C, 0x25); 1453 hdptx_write(hdptx, CMN_REG005D, 0x0c); 1454 hdptx_update_bits(hdptx, CMN_REG005E, ROPLL_SDM_EN_MASK, 1455 ROPLL_SDM_EN(cfg->sdm_en)); 1456 if (!cfg->sdm_en) 1457 hdptx_update_bits(hdptx, CMN_REG005E, 0xf, 0); 1458 hdptx_write(hdptx, CMN_REG005F, 0x01); 1459 hdptx_update_bits(hdptx, CMN_REG0064, ROPLL_SDM_NUM_SIGN_RBR_MASK, 1460 ROPLL_SDM_NUM_SIGN_RBR(cfg->sdm_num_sign)); 1461 hdptx_write(hdptx, CMN_REG0065, cfg->sdm_num); 1462 hdptx_write(hdptx, CMN_REG0060, cfg->sdm_deno); 1463 hdptx_update_bits(hdptx, CMN_REG0069, ROPLL_SDC_N_RBR_MASK, 1464 ROPLL_SDC_N_RBR(cfg->sdc_n)); 1465 hdptx_write(hdptx, CMN_REG006C, cfg->sdc_num); 1466 hdptx_write(hdptx, CMN_REG0070, cfg->sdc_deno); 1467 hdptx_write(hdptx, CMN_REG006B, 0x04); 1468 hdptx_write(hdptx, CMN_REG0073, 0x30); 1469 hdptx_write(hdptx, CMN_REG0074, 0x00); 1470 hdptx_write(hdptx, CMN_REG0075, 0x20); 1471 hdptx_write(hdptx, CMN_REG0076, 0x30); 1472 hdptx_write(hdptx, CMN_REG0077, 0x08); 1473 hdptx_write(hdptx, CMN_REG0078, 0x0c); 1474 hdptx_write(hdptx, CMN_REG0079, 0x00); 1475 hdptx_write(hdptx, CMN_REG007B, 0x00); 1476 hdptx_write(hdptx, CMN_REG007C, 0x00); 1477 hdptx_write(hdptx, CMN_REG007D, 0x00); 1478 hdptx_write(hdptx, CMN_REG007E, 0x00); 1479 hdptx_write(hdptx, CMN_REG007F, 0x00); 1480 hdptx_write(hdptx, CMN_REG0080, 0x00); 1481 hdptx_write(hdptx, CMN_REG0081, 0x09); 1482 hdptx_write(hdptx, CMN_REG0082, 0x04); 1483 hdptx_write(hdptx, CMN_REG0083, 0x24); 1484 hdptx_write(hdptx, CMN_REG0084, 0x20); 1485 hdptx_write(hdptx, CMN_REG0085, 0x03); 1486 hdptx_write(hdptx, CMN_REG0086, 0x01); 1487 hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_POSTDIV_SEL_MASK, 1488 PLL_PCG_POSTDIV_SEL(cfg->pms_sdiv)); 1489 hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_CLK_SEL_MASK, 1490 PLL_PCG_CLK_SEL(color_depth)); 1491 hdptx_write(hdptx, CMN_REG0087, 0x0c); 1492 hdptx_write(hdptx, CMN_REG0089, 0x00); 1493 hdptx_write(hdptx, CMN_REG008A, 0x55); 1494 hdptx_write(hdptx, CMN_REG008B, 0x25); 1495 hdptx_write(hdptx, CMN_REG008C, 0x2c); 1496 hdptx_write(hdptx, CMN_REG008D, 0x22); 1497 hdptx_write(hdptx, CMN_REG008E, 0x14); 1498 hdptx_write(hdptx, CMN_REG008F, 0x20); 1499 hdptx_write(hdptx, CMN_REG0090, 0x00); 1500 hdptx_write(hdptx, CMN_REG0091, 0x00); 1501 hdptx_write(hdptx, CMN_REG0092, 0x00); 1502 hdptx_write(hdptx, CMN_REG0093, 0x00); 1503 hdptx_write(hdptx, CMN_REG0094, 0x00); 1504 hdptx_write(hdptx, CMN_REG0097, 0x02); 1505 hdptx_write(hdptx, CMN_REG0099, 0x04); 1506 hdptx_write(hdptx, CMN_REG009A, 0x11); 1507 hdptx_write(hdptx, CMN_REG009B, 0x10); 1508 hdptx_write(hdptx, SB_REG0114, 0x00); 1509 hdptx_write(hdptx, SB_REG0115, 0x00); 1510 hdptx_write(hdptx, SB_REG0116, 0x00); 1511 hdptx_write(hdptx, SB_REG0117, 0x00); 1512 hdptx_write(hdptx, LNTOP_REG0200, 0x04); 1513 hdptx_write(hdptx, LNTOP_REG0201, 0x00); 1514 hdptx_write(hdptx, LNTOP_REG0202, 0x00); 1515 hdptx_write(hdptx, LNTOP_REG0203, 0xf0); 1516 hdptx_write(hdptx, LNTOP_REG0204, 0xff); 1517 hdptx_write(hdptx, LNTOP_REG0205, 0xff); 1518 hdptx_write(hdptx, LNTOP_REG0206, 0x05); 1519 hdptx_write(hdptx, LNTOP_REG0207, 0x0f); 1520 hdptx_write(hdptx, LANE_REG0303, 0x0c); 1521 hdptx_write(hdptx, LANE_REG0307, 0x20); 1522 hdptx_write(hdptx, LANE_REG030A, 0x17); 1523 hdptx_write(hdptx, LANE_REG030B, 0x77); 1524 hdptx_write(hdptx, LANE_REG030C, 0x77); 1525 hdptx_write(hdptx, LANE_REG030D, 0x77); 1526 hdptx_write(hdptx, LANE_REG030E, 0x38); 1527 hdptx_write(hdptx, LANE_REG0310, 0x03); 1528 hdptx_write(hdptx, LANE_REG0311, 0x0f); 1529 hdptx_write(hdptx, LANE_REG0312, 0x3c); 1530 hdptx_write(hdptx, LANE_REG0316, 0x02); 1531 hdptx_write(hdptx, LANE_REG031B, 0x01); 1532 hdptx_write(hdptx, LANE_REG031F, 0x15); 1533 hdptx_write(hdptx, LANE_REG0320, 0xa0); 1534 hdptx_write(hdptx, LANE_REG0403, 0x0c); 1535 hdptx_write(hdptx, LANE_REG0407, 0x20); 1536 hdptx_write(hdptx, LANE_REG040A, 0x17); 1537 hdptx_write(hdptx, LANE_REG040B, 0x77); 1538 hdptx_write(hdptx, LANE_REG040C, 0x77); 1539 hdptx_write(hdptx, LANE_REG040D, 0x77); 1540 hdptx_write(hdptx, LANE_REG040E, 0x38); 1541 hdptx_write(hdptx, LANE_REG0410, 0x03); 1542 hdptx_write(hdptx, LANE_REG0411, 0x0f); 1543 hdptx_write(hdptx, LANE_REG0412, 0x3c); 1544 hdptx_write(hdptx, LANE_REG0416, 0x02); 1545 hdptx_write(hdptx, LANE_REG041B, 0x01); 1546 hdptx_write(hdptx, LANE_REG041F, 0x15); 1547 hdptx_write(hdptx, LANE_REG0420, 0xa0); 1548 hdptx_write(hdptx, LANE_REG0503, 0x0c); 1549 hdptx_write(hdptx, LANE_REG0507, 0x20); 1550 hdptx_write(hdptx, LANE_REG050A, 0x17); 1551 hdptx_write(hdptx, LANE_REG050B, 0x77); 1552 hdptx_write(hdptx, LANE_REG050C, 0x77); 1553 hdptx_write(hdptx, LANE_REG050D, 0x77); 1554 hdptx_write(hdptx, LANE_REG050E, 0x38); 1555 hdptx_write(hdptx, LANE_REG0510, 0x03); 1556 hdptx_write(hdptx, LANE_REG0511, 0x0f); 1557 hdptx_write(hdptx, LANE_REG0512, 0x3c); 1558 hdptx_write(hdptx, LANE_REG0516, 0x02); 1559 hdptx_write(hdptx, LANE_REG051B, 0x01); 1560 hdptx_write(hdptx, LANE_REG051F, 0x15); 1561 hdptx_write(hdptx, LANE_REG0520, 0xa0); 1562 hdptx_write(hdptx, LANE_REG0603, 0x0c); 1563 hdptx_write(hdptx, LANE_REG0607, 0x20); 1564 hdptx_write(hdptx, LANE_REG060A, 0x17); 1565 hdptx_write(hdptx, LANE_REG060B, 0x77); 1566 hdptx_write(hdptx, LANE_REG060C, 0x77); 1567 hdptx_write(hdptx, LANE_REG060D, 0x77); 1568 hdptx_write(hdptx, LANE_REG060E, 0x38); 1569 hdptx_write(hdptx, LANE_REG0610, 0x03); 1570 hdptx_write(hdptx, LANE_REG0611, 0x0f); 1571 hdptx_write(hdptx, LANE_REG0612, 0x3c); 1572 hdptx_write(hdptx, LANE_REG0616, 0x02); 1573 hdptx_write(hdptx, LANE_REG061B, 0x01); 1574 hdptx_write(hdptx, LANE_REG061F, 0x15); 1575 hdptx_write(hdptx, LANE_REG0620, 0xa0); 1576 1577 hdptx_write(hdptx, LANE_REG0303, 0x2f); 1578 hdptx_write(hdptx, LANE_REG0403, 0x2f); 1579 hdptx_write(hdptx, LANE_REG0503, 0x2f); 1580 hdptx_write(hdptx, LANE_REG0603, 0x2f); 1581 hdptx_write(hdptx, LANE_REG0305, 0x03); 1582 hdptx_write(hdptx, LANE_REG0405, 0x03); 1583 hdptx_write(hdptx, LANE_REG0505, 0x03); 1584 hdptx_write(hdptx, LANE_REG0605, 0x03); 1585 hdptx_write(hdptx, LANE_REG0306, 0xfc); 1586 hdptx_write(hdptx, LANE_REG0406, 0xfc); 1587 hdptx_write(hdptx, LANE_REG0506, 0xfc); 1588 hdptx_write(hdptx, LANE_REG0606, 0xfc); 1589 1590 hdptx_write(hdptx, LANE_REG0305, 0x4f); 1591 hdptx_write(hdptx, LANE_REG0405, 0x4f); 1592 hdptx_write(hdptx, LANE_REG0505, 0x4f); 1593 hdptx_write(hdptx, LANE_REG0605, 0x4f); 1594 hdptx_write(hdptx, LANE_REG0304, 0x14); 1595 hdptx_write(hdptx, LANE_REG0404, 0x14); 1596 hdptx_write(hdptx, LANE_REG0504, 0x14); 1597 hdptx_write(hdptx, LANE_REG0604, 0x14); 1598 1599 return hdptx_post_power_up(hdptx); 1600 } 1601 1602 static int hdptx_lcpll_frl_mode_config(struct rockchip_hdptx_phy *hdptx, u32 rate) 1603 { 1604 u32 bit_rate = rate & DATA_RATE_MASK; 1605 u8 color_depth = (rate & COLOR_DEPTH_MASK) ? 1 : 0; 1606 struct lcpll_config *cfg = lcpll_cfg; 1607 1608 for (; cfg->bit_rate != ~0; cfg++) 1609 if (bit_rate == cfg->bit_rate) 1610 break; 1611 1612 if (cfg->bit_rate == ~0) 1613 return -EINVAL; 1614 1615 hdptx_pre_power_up(hdptx); 1616 1617 hdptx_update_bits(hdptx, CMN_REG0008, LCPLL_EN_MASK | 1618 LCPLL_LCVCO_MODE_EN_MASK, LCPLL_EN(1) | 1619 LCPLL_LCVCO_MODE_EN(cfg->lcvco_mode_en)); 1620 hdptx_write(hdptx, CMN_REG0009, 0x0c); 1621 hdptx_write(hdptx, CMN_REG000A, 0x83); 1622 hdptx_write(hdptx, CMN_REG000B, 0x06); 1623 hdptx_write(hdptx, CMN_REG000C, 0x20); 1624 hdptx_write(hdptx, CMN_REG000D, 0xb8); 1625 hdptx_write(hdptx, CMN_REG000E, 0x0f); 1626 hdptx_write(hdptx, CMN_REG000F, 0x0f); 1627 hdptx_write(hdptx, CMN_REG0010, 0x04); 1628 hdptx_write(hdptx, CMN_REG0011, 0x00); 1629 hdptx_write(hdptx, CMN_REG0012, 0x26); 1630 hdptx_write(hdptx, CMN_REG0013, 0x22); 1631 hdptx_write(hdptx, CMN_REG0014, 0x24); 1632 hdptx_write(hdptx, CMN_REG0015, 0x77); 1633 hdptx_write(hdptx, CMN_REG0016, 0x08); 1634 hdptx_write(hdptx, CMN_REG0017, 0x00); 1635 hdptx_write(hdptx, CMN_REG0018, 0x04); 1636 hdptx_write(hdptx, CMN_REG0019, 0x48); 1637 hdptx_write(hdptx, CMN_REG001A, 0x01); 1638 hdptx_write(hdptx, CMN_REG001B, 0x00); 1639 hdptx_write(hdptx, CMN_REG001C, 0x01); 1640 hdptx_write(hdptx, CMN_REG001D, 0x64); 1641 hdptx_update_bits(hdptx, CMN_REG001E, LCPLL_PI_EN_MASK | 1642 LCPLL_100M_CLK_EN_MASK, 1643 LCPLL_PI_EN(cfg->pi_en) | 1644 LCPLL_100M_CLK_EN(cfg->clk_en_100m)); 1645 hdptx_write(hdptx, CMN_REG001F, 0x00); 1646 hdptx_write(hdptx, CMN_REG0020, cfg->pms_mdiv); 1647 hdptx_write(hdptx, CMN_REG0021, cfg->pms_mdiv_afc); 1648 hdptx_write(hdptx, CMN_REG0022, (cfg->pms_pdiv << 4) | cfg->pms_refdiv); 1649 hdptx_write(hdptx, CMN_REG0023, (cfg->pms_sdiv << 4) | cfg->pms_sdiv); 1650 hdptx_write(hdptx, CMN_REG0025, 0x10); 1651 hdptx_write(hdptx, CMN_REG0026, 0x53); 1652 hdptx_write(hdptx, CMN_REG0027, 0x01); 1653 hdptx_write(hdptx, CMN_REG0028, 0x0d); 1654 hdptx_write(hdptx, CMN_REG0029, 0x01); 1655 hdptx_write(hdptx, CMN_REG002A, cfg->sdm_deno); 1656 hdptx_write(hdptx, CMN_REG002B, cfg->sdm_num_sign); 1657 hdptx_write(hdptx, CMN_REG002C, cfg->sdm_num); 1658 hdptx_update_bits(hdptx, CMN_REG002D, LCPLL_SDC_N_MASK, 1659 LCPLL_SDC_N(cfg->sdc_n)); 1660 hdptx_write(hdptx, CMN_REG002E, 0x02); 1661 hdptx_write(hdptx, CMN_REG002F, 0x0d); 1662 hdptx_write(hdptx, CMN_REG0030, 0x00); 1663 hdptx_write(hdptx, CMN_REG0031, 0x20); 1664 hdptx_write(hdptx, CMN_REG0032, 0x30); 1665 hdptx_write(hdptx, CMN_REG0033, 0x0b); 1666 hdptx_write(hdptx, CMN_REG0034, 0x23); 1667 hdptx_write(hdptx, CMN_REG0035, 0x00); 1668 hdptx_write(hdptx, CMN_REG0038, 0x00); 1669 hdptx_write(hdptx, CMN_REG0039, 0x00); 1670 hdptx_write(hdptx, CMN_REG003A, 0x00); 1671 hdptx_write(hdptx, CMN_REG003B, 0x00); 1672 hdptx_write(hdptx, CMN_REG003C, 0x80); 1673 hdptx_write(hdptx, CMN_REG003D, 0x00); 1674 hdptx_write(hdptx, CMN_REG003E, 0x0c); 1675 hdptx_write(hdptx, CMN_REG003F, 0x83); 1676 hdptx_write(hdptx, CMN_REG0040, 0x06); 1677 hdptx_write(hdptx, CMN_REG0041, 0x20); 1678 hdptx_write(hdptx, CMN_REG0042, 0xb8); 1679 hdptx_write(hdptx, CMN_REG0043, 0x00); 1680 hdptx_write(hdptx, CMN_REG0044, 0x46); 1681 hdptx_write(hdptx, CMN_REG0045, 0x24); 1682 hdptx_write(hdptx, CMN_REG0046, 0xff); 1683 hdptx_write(hdptx, CMN_REG0047, 0x00); 1684 hdptx_write(hdptx, CMN_REG0048, 0x44); 1685 hdptx_write(hdptx, CMN_REG0049, 0xfa); 1686 hdptx_write(hdptx, CMN_REG004A, 0x08); 1687 hdptx_write(hdptx, CMN_REG004B, 0x00); 1688 hdptx_write(hdptx, CMN_REG004C, 0x01); 1689 hdptx_write(hdptx, CMN_REG004D, 0x64); 1690 hdptx_write(hdptx, CMN_REG004E, 0x14); 1691 hdptx_write(hdptx, CMN_REG004F, 0x00); 1692 hdptx_write(hdptx, CMN_REG0050, 0x00); 1693 hdptx_write(hdptx, CMN_REG0051, 0x00); 1694 hdptx_write(hdptx, CMN_REG0055, 0x00); 1695 hdptx_write(hdptx, CMN_REG0059, 0x11); 1696 hdptx_write(hdptx, CMN_REG005A, 0x03); 1697 hdptx_write(hdptx, CMN_REG005C, 0x05); 1698 hdptx_write(hdptx, CMN_REG005D, 0x0c); 1699 hdptx_write(hdptx, CMN_REG005E, 0x07); 1700 hdptx_write(hdptx, CMN_REG005F, 0x01); 1701 hdptx_write(hdptx, CMN_REG0060, 0x01); 1702 hdptx_write(hdptx, CMN_REG0064, 0x07); 1703 hdptx_write(hdptx, CMN_REG0065, 0x00); 1704 hdptx_write(hdptx, CMN_REG0069, 0x00); 1705 hdptx_write(hdptx, CMN_REG006B, 0x04); 1706 hdptx_write(hdptx, CMN_REG006C, 0x00); 1707 hdptx_write(hdptx, CMN_REG0070, 0x01); 1708 hdptx_write(hdptx, CMN_REG0073, 0x30); 1709 hdptx_write(hdptx, CMN_REG0074, 0x00); 1710 hdptx_write(hdptx, CMN_REG0075, 0x20); 1711 hdptx_write(hdptx, CMN_REG0076, 0x30); 1712 hdptx_write(hdptx, CMN_REG0077, 0x08); 1713 hdptx_write(hdptx, CMN_REG0078, 0x0c); 1714 hdptx_write(hdptx, CMN_REG0079, 0x00); 1715 hdptx_write(hdptx, CMN_REG007B, 0x00); 1716 hdptx_write(hdptx, CMN_REG007C, 0x00); 1717 hdptx_write(hdptx, CMN_REG007D, 0x00); 1718 hdptx_write(hdptx, CMN_REG007E, 0x00); 1719 hdptx_write(hdptx, CMN_REG007F, 0x00); 1720 hdptx_write(hdptx, CMN_REG0080, 0x00); 1721 hdptx_write(hdptx, CMN_REG0081, 0x09); 1722 hdptx_write(hdptx, CMN_REG0082, 0x04); 1723 hdptx_write(hdptx, CMN_REG0083, 0x24); 1724 hdptx_write(hdptx, CMN_REG0084, 0x20); 1725 hdptx_write(hdptx, CMN_REG0085, 0x03); 1726 hdptx_write(hdptx, CMN_REG0086, 0x01); 1727 hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_POSTDIV_SEL_MASK, 1728 PLL_PCG_POSTDIV_SEL(cfg->pms_sdiv)); 1729 hdptx_update_bits(hdptx, CMN_REG0086, PLL_PCG_CLK_SEL_MASK, 1730 PLL_PCG_CLK_SEL(color_depth)); 1731 hdptx_write(hdptx, CMN_REG0087, 0x0c); 1732 hdptx_write(hdptx, CMN_REG0089, 0x02); 1733 hdptx_write(hdptx, CMN_REG008A, 0x55); 1734 hdptx_write(hdptx, CMN_REG008B, 0x25); 1735 hdptx_write(hdptx, CMN_REG008C, 0x2c); 1736 hdptx_write(hdptx, CMN_REG008D, 0x22); 1737 hdptx_write(hdptx, CMN_REG008E, 0x14); 1738 hdptx_write(hdptx, CMN_REG008F, 0x20); 1739 hdptx_write(hdptx, CMN_REG0090, 0x00); 1740 hdptx_write(hdptx, CMN_REG0091, 0x00); 1741 hdptx_write(hdptx, CMN_REG0092, 0x00); 1742 hdptx_write(hdptx, CMN_REG0093, 0x00); 1743 hdptx_write(hdptx, CMN_REG0095, 0x00); 1744 hdptx_write(hdptx, CMN_REG0097, 0x00); 1745 hdptx_write(hdptx, CMN_REG0099, 0x00); 1746 hdptx_write(hdptx, CMN_REG009A, 0x11); 1747 hdptx_write(hdptx, CMN_REG009B, 0x10); 1748 hdptx_write(hdptx, SB_REG0114, 0x00); 1749 hdptx_write(hdptx, SB_REG0115, 0x00); 1750 hdptx_write(hdptx, SB_REG0116, 0x00); 1751 hdptx_write(hdptx, SB_REG0117, 0x00); 1752 hdptx_write(hdptx, LNTOP_REG0200, 0x04); 1753 hdptx_write(hdptx, LNTOP_REG0201, 0x00); 1754 hdptx_write(hdptx, LNTOP_REG0202, 0x00); 1755 hdptx_write(hdptx, LNTOP_REG0203, 0xf0); 1756 hdptx_write(hdptx, LNTOP_REG0204, 0xff); 1757 hdptx_write(hdptx, LNTOP_REG0205, 0xff); 1758 hdptx_write(hdptx, LNTOP_REG0206, 0x05); 1759 hdptx_write(hdptx, LNTOP_REG0207, 0x0f); 1760 hdptx_write(hdptx, LANE_REG0303, 0x0c); 1761 hdptx_write(hdptx, LANE_REG0307, 0x20); 1762 hdptx_write(hdptx, LANE_REG030A, 0x17); 1763 hdptx_write(hdptx, LANE_REG030B, 0x77); 1764 hdptx_write(hdptx, LANE_REG030C, 0x77); 1765 hdptx_write(hdptx, LANE_REG030D, 0x77); 1766 hdptx_write(hdptx, LANE_REG030E, 0x38); 1767 hdptx_write(hdptx, LANE_REG0310, 0x03); 1768 hdptx_write(hdptx, LANE_REG0311, 0x0f); 1769 hdptx_write(hdptx, LANE_REG0312, 0x3c); 1770 hdptx_write(hdptx, LANE_REG0316, 0x02); 1771 hdptx_write(hdptx, LANE_REG031B, 0x01); 1772 hdptx_write(hdptx, LANE_REG031F, 0x15); 1773 hdptx_write(hdptx, LANE_REG0320, 0xa0); 1774 hdptx_write(hdptx, LANE_REG0403, 0x0c); 1775 hdptx_write(hdptx, LANE_REG0407, 0x20); 1776 hdptx_write(hdptx, LANE_REG040A, 0x17); 1777 hdptx_write(hdptx, LANE_REG040B, 0x77); 1778 hdptx_write(hdptx, LANE_REG040C, 0x77); 1779 hdptx_write(hdptx, LANE_REG040D, 0x77); 1780 hdptx_write(hdptx, LANE_REG040E, 0x38); 1781 hdptx_write(hdptx, LANE_REG0410, 0x03); 1782 hdptx_write(hdptx, LANE_REG0411, 0x0f); 1783 hdptx_write(hdptx, LANE_REG0412, 0x3c); 1784 hdptx_write(hdptx, LANE_REG0416, 0x02); 1785 hdptx_write(hdptx, LANE_REG041B, 0x01); 1786 hdptx_write(hdptx, LANE_REG041F, 0x15); 1787 hdptx_write(hdptx, LANE_REG0420, 0xa0); 1788 hdptx_write(hdptx, LANE_REG0503, 0x0c); 1789 hdptx_write(hdptx, LANE_REG0507, 0x20); 1790 hdptx_write(hdptx, LANE_REG050A, 0x17); 1791 hdptx_write(hdptx, LANE_REG050B, 0x77); 1792 hdptx_write(hdptx, LANE_REG050C, 0x77); 1793 hdptx_write(hdptx, LANE_REG050D, 0x77); 1794 hdptx_write(hdptx, LANE_REG050E, 0x38); 1795 hdptx_write(hdptx, LANE_REG0510, 0x03); 1796 hdptx_write(hdptx, LANE_REG0511, 0x0f); 1797 hdptx_write(hdptx, LANE_REG0512, 0x3c); 1798 hdptx_write(hdptx, LANE_REG0516, 0x02); 1799 hdptx_write(hdptx, LANE_REG051B, 0x01); 1800 hdptx_write(hdptx, LANE_REG051F, 0x15); 1801 hdptx_write(hdptx, LANE_REG0520, 0xa0); 1802 hdptx_write(hdptx, LANE_REG0603, 0x0c); 1803 hdptx_write(hdptx, LANE_REG0607, 0x20); 1804 hdptx_write(hdptx, LANE_REG060A, 0x17); 1805 hdptx_write(hdptx, LANE_REG060B, 0x77); 1806 hdptx_write(hdptx, LANE_REG060C, 0x77); 1807 hdptx_write(hdptx, LANE_REG060D, 0x77); 1808 hdptx_write(hdptx, LANE_REG060E, 0x38); 1809 hdptx_write(hdptx, LANE_REG0610, 0x03); 1810 hdptx_write(hdptx, LANE_REG0611, 0x0f); 1811 hdptx_write(hdptx, LANE_REG0612, 0x3c); 1812 hdptx_write(hdptx, LANE_REG0616, 0x02); 1813 hdptx_write(hdptx, LANE_REG061B, 0x01); 1814 hdptx_write(hdptx, LANE_REG061F, 0x15); 1815 hdptx_write(hdptx, LANE_REG0620, 0xa0); 1816 1817 return hdptx_post_power_up(hdptx); 1818 } 1819 1820 static int rockchip_hdptx_phy_power_on(struct rockchip_phy *phy) 1821 { 1822 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 1823 int bus_width = hdptx->bus_width; 1824 int bit_rate = bus_width & DATA_RATE_MASK; 1825 1826 printf("bus_width:0x%x,bit_rate:%d\n", bus_width, bit_rate); 1827 1828 if (bus_width & HDMI_MODE_MASK) 1829 if (bit_rate > 24000000) 1830 return hdptx_lcpll_frl_mode_config(hdptx, bus_width); 1831 else 1832 return hdptx_ropll_frl_mode_config(hdptx, bus_width); 1833 else 1834 return hdptx_ropll_tmds_mode_config(hdptx, bus_width); 1835 } 1836 1837 static int rockchip_hdptx_phy_power_off(struct rockchip_phy *phy) 1838 { 1839 return 0; 1840 } 1841 1842 static long rockchip_hdptx_phy_clk_round_rate(struct rockchip_phy *phy, 1843 unsigned long rate) 1844 { 1845 struct ropll_config *cfg = ropll_tmds_cfg; 1846 u32 bit_rate = rate / 100; 1847 1848 for (; cfg->bit_rate != ~0; cfg++) 1849 if (bit_rate == cfg->bit_rate) 1850 break; 1851 1852 if (cfg->bit_rate == ~0 && !hdptx_phy_clk_pll_calc(bit_rate, NULL)) 1853 return -EINVAL; 1854 1855 return rate; 1856 } 1857 1858 static unsigned long rockchip_hdptx_phy_clk_set_rate(struct rockchip_phy *phy, 1859 unsigned long rate) 1860 { 1861 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 1862 int bus_width = hdptx->bus_width; 1863 u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; 1864 1865 if (color_depth) 1866 rate = (rate / 100) * 5 / 4; 1867 else 1868 rate = rate / 100; 1869 return hdptx_ropll_cmn_config(hdptx, rate); 1870 } 1871 1872 static int 1873 rockchip_hdptx_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width) 1874 { 1875 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 1876 1877 hdptx->bus_width = bus_width; 1878 1879 return 0; 1880 } 1881 1882 const struct rockchip_phy_funcs hdptx_hdmi_phy_funcs = { 1883 .power_on = rockchip_hdptx_phy_power_on, 1884 .power_off = rockchip_hdptx_phy_power_off, 1885 .set_pll = rockchip_hdptx_phy_clk_set_rate, 1886 .set_bus_width = rockchip_hdptx_phy_set_bus_width, 1887 .round_rate = rockchip_hdptx_phy_clk_round_rate, 1888 }; 1889 1890 static struct rockchip_phy hdptx_hdmi_phy_driver_data0 = { 1891 .funcs = &hdptx_hdmi_phy_funcs, 1892 }; 1893 1894 static struct rockchip_phy hdptx_hdmi_phy_driver_data1 = { 1895 .funcs = &hdptx_hdmi_phy_funcs, 1896 }; 1897 1898 static int rockchip_hdptx_phy_hdmi_probe(struct udevice *dev) 1899 { 1900 struct rockchip_hdptx_phy *hdptx = dev_get_priv(dev); 1901 struct rockchip_phy *phy; 1902 struct udevice *syscon; 1903 int ret; 1904 1905 hdptx->id = of_alias_get_id(ofnode_to_np(dev->node), "hdptxhdmi"); 1906 if (hdptx->id < 0) 1907 hdptx->id = 0; 1908 1909 if (!hdptx->id) { 1910 g_hdptx0 = hdptx; 1911 dev->driver_data = (ulong)&hdptx_hdmi_phy_driver_data0; 1912 phy = &hdptx_hdmi_phy_driver_data0; 1913 } else { 1914 g_hdptx1 = hdptx; 1915 dev->driver_data = (ulong)&hdptx_hdmi_phy_driver_data1; 1916 phy = &hdptx_hdmi_phy_driver_data1; 1917 } 1918 1919 hdptx->base = dev_read_addr_ptr(dev); 1920 if (!hdptx->base) 1921 return -ENOENT; 1922 1923 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1924 &syscon); 1925 if (ret) 1926 return ret; 1927 1928 hdptx->grf = syscon_get_regmap(syscon); 1929 if (IS_ERR(hdptx->grf)) { 1930 ret = PTR_ERR(hdptx->grf); 1931 dev_err(dev, "unable to find regmap: %d\n", ret); 1932 return ret; 1933 } 1934 1935 hdptx->dev = dev; 1936 phy->dev = dev; 1937 1938 ret = reset_get_by_name(dev, "apb", &hdptx->apb_reset); 1939 if (ret < 0) { 1940 dev_err(dev, "failed to get apb reset: %d\n", ret); 1941 return ret; 1942 } 1943 1944 ret = reset_get_by_name(dev, "init", &hdptx->init_reset); 1945 if (ret < 0) { 1946 dev_err(dev, "failed to get init reset: %d\n", ret); 1947 return ret; 1948 } 1949 1950 ret = reset_get_by_name(dev, "cmn", &hdptx->cmn_reset); 1951 if (ret < 0) { 1952 dev_err(dev, "failed to get cmn reset: %d\n", ret); 1953 return ret; 1954 } 1955 1956 ret = reset_get_by_name(dev, "lane", &hdptx->lane_reset); 1957 if (ret < 0) { 1958 dev_err(dev, "failed to get lane reset: %d\n", ret); 1959 return ret; 1960 } 1961 1962 ret = reset_get_by_name(dev, "ropll", &hdptx->ropll_reset); 1963 if (ret < 0) { 1964 dev_err(dev, "failed to get ropll reset: %d\n", ret); 1965 return ret; 1966 } 1967 1968 ret = reset_get_by_name(dev, "lcpll", &hdptx->lcpll_reset); 1969 if (ret < 0) { 1970 dev_err(dev, "failed to get lane reset: %d\n", ret); 1971 return ret; 1972 } 1973 1974 return 0; 1975 } 1976 1977 static int rockchip_hdptx_phy_hdmi_bind(struct udevice *parent) 1978 { 1979 struct udevice *child; 1980 ofnode subnode; 1981 char name[30], *str; 1982 int id, ret; 1983 1984 id = of_alias_get_id(ofnode_to_np(parent->node), "hdptxhdmi"); 1985 if (id < 0) 1986 id = 0; 1987 1988 sprintf(name, "hdmiphypll_clk%d", id); 1989 str = strdup(name); 1990 1991 subnode = ofnode_find_subnode(parent->node, "clk-port"); 1992 if (!ofnode_valid(subnode)) { 1993 printf("%s: no subnode for %s", __func__, parent->name); 1994 return -ENXIO; 1995 } 1996 1997 ret = device_bind_driver_to_node(parent, "clk_hdptx", str, subnode, &child); 1998 if (ret) { 1999 printf("%s: clk-port cannot bind its driver\n", __func__); 2000 return ret; 2001 } 2002 2003 return 0; 2004 } 2005 2006 static const struct udevice_id rockchip_hdptx_phy_hdmi_ids[] = { 2007 { .compatible = "rockchip,rk3588-hdptx-phy-hdmi", 2008 .data = (ulong)&hdptx_hdmi_phy_driver_data0, 2009 }, 2010 {} 2011 }; 2012 2013 U_BOOT_DRIVER(rockchip_hdptx_phy_hdmi) = { 2014 .name = "rockchip_hdptx_phy_hdmi", 2015 .id = UCLASS_PHY, 2016 .of_match = rockchip_hdptx_phy_hdmi_ids, 2017 .probe = rockchip_hdptx_phy_hdmi_probe, 2018 .bind = rockchip_hdptx_phy_hdmi_bind, 2019 .priv_auto_alloc_size = sizeof(struct rockchip_hdptx_phy), 2020 }; 2021 2022 static struct rockchip_hdptx_phy *get_hdptx(struct udevice *dev) 2023 { 2024 if (!strcmp(dev->name, "hdmiphypll_clk0")) 2025 return g_hdptx0; 2026 2027 return g_hdptx1; 2028 } 2029 2030 static ulong hdptx_clk_get_rate(struct clk *clk) 2031 { 2032 struct clk_hdptx *priv = dev_get_priv(clk->dev); 2033 2034 return priv->rate; 2035 } 2036 2037 static ulong hdptx_clk_set_rate(struct clk *clk, ulong rate) 2038 { 2039 struct clk_hdptx *priv = dev_get_priv(clk->dev); 2040 struct rockchip_hdptx_phy *hdptx = get_hdptx(clk->dev); 2041 int bus_width = hdptx->bus_width; 2042 u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; 2043 ulong new_rate = -ENOENT; 2044 2045 if (color_depth) 2046 rate = (rate / 100) * 5 / 4; 2047 else 2048 rate = rate / 100; 2049 if (!hdptx_ropll_cmn_config(hdptx, rate)) { 2050 new_rate = rate; 2051 priv->rate = rate; 2052 } 2053 2054 return new_rate; 2055 } 2056 2057 static const struct clk_ops hdptx_clk_ops = { 2058 .get_rate = hdptx_clk_get_rate, 2059 .set_rate = hdptx_clk_set_rate, 2060 }; 2061 2062 static int hdptx_clk_probe(struct udevice *dev) 2063 { 2064 return 0; 2065 } 2066 2067 /* 2068 * In order for other display interfaces to use hdmiphy as source 2069 * for dclk, hdmiphy must register a virtual clock driver 2070 */ 2071 U_BOOT_DRIVER(clk_hdptx) = { 2072 .name = "clk_hdptx", 2073 .id = UCLASS_CLK, 2074 .priv_auto_alloc_size = sizeof(struct clk_hdptx), 2075 .ops = &hdptx_clk_ops, 2076 .probe = hdptx_clk_probe, 2077 }; 2078