1 /* 2 * Analogix DP (Display port) core register interface driver. 3 * 4 * Copyright (C) 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <errno.h> 17 #include <malloc.h> 18 #include <asm/unaligned.h> 19 #include <linux/list.h> 20 #include <dm/device.h> 21 #include <syscon.h> 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 #include "analogix_dp.h" 29 30 #define COMMON_INT_MASK_1 0 31 #define COMMON_INT_MASK_2 0 32 #define COMMON_INT_MASK_3 0 33 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 34 #define INT_STA_MASK INT_HPD 35 36 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) 37 { 38 readl(dp->reg_base); 39 writel(val, dp->reg_base + reg); 40 writel(val, dp->reg_base + reg); 41 } 42 43 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) 44 { 45 readl(dp->reg_base + reg); 46 47 return readl(dp->reg_base + reg); 48 } 49 50 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 51 { 52 u32 reg; 53 54 if (enable) { 55 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 56 reg |= HDCP_VIDEO_MUTE; 57 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 58 } else { 59 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 60 reg &= ~HDCP_VIDEO_MUTE; 61 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 62 } 63 } 64 65 void analogix_dp_stop_video(struct analogix_dp_device *dp) 66 { 67 u32 reg; 68 69 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 70 reg &= ~VIDEO_EN; 71 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 72 } 73 74 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) 75 { 76 u32 reg; 77 78 if (enable) 79 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | 80 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; 81 else 82 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | 83 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; 84 85 analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg); 86 } 87 88 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 89 { 90 u32 reg; 91 92 reg = TX_TERMINAL_CTRL_50_OHM; 93 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_1, reg); 94 95 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 96 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_2, reg); 97 98 if (dp->plat_data.dev_type == ROCKCHIP_DP) { 99 reg = REF_CLK_24M; 100 if (dp->plat_data.subdev_type == RK3288_DP || 101 dp->plat_data.subdev_type == RK3368_EDP) 102 reg ^= REF_CLK_MASK; 103 104 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg); 105 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x95); 106 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40); 107 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58); 108 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22); 109 } 110 111 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 112 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_3, reg); 113 114 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 115 TX_CUR1_2X | TX_CUR_16_MA; 116 analogix_dp_write(dp, ANALOGIX_DP_PLL_FILTER_CTL_1, reg); 117 118 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 119 CH1_AMP_400_MV | CH0_AMP_400_MV; 120 analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg); 121 } 122 123 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 124 { 125 /* Set interrupt pin assertion polarity as high */ 126 analogix_dp_write(dp, ANALOGIX_DP_INT_CTL, INT_POL1 | INT_POL0); 127 128 /* Clear pending regisers */ 129 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff); 130 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f); 131 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0); 132 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7); 133 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63); 134 135 /* 0:mask,1: unmask */ 136 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00); 137 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00); 138 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00); 139 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00); 140 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00); 141 } 142 143 void analogix_dp_reset(struct analogix_dp_device *dp) 144 { 145 u32 reg; 146 147 analogix_dp_stop_video(dp); 148 analogix_dp_enable_video_mute(dp, 0); 149 150 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 151 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 152 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 153 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 154 155 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 156 SERDES_FIFO_FUNC_EN_N | 157 LS_CLK_DOMAIN_FUNC_EN_N; 158 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 159 160 udelay(30); 161 162 analogix_dp_lane_swap(dp, 0); 163 164 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0); 165 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40); 166 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0); 167 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0); 168 169 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0); 170 analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0); 171 172 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e); 173 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a); 174 175 analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10); 176 177 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0); 178 179 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0); 180 analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20); 181 182 analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4); 183 analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2); 184 185 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101); 186 } 187 188 void analogix_dp_swreset(struct analogix_dp_device *dp) 189 { 190 analogix_dp_write(dp, ANALOGIX_DP_TX_SW_RESET, RESET_DP_TX); 191 } 192 193 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 194 { 195 u32 reg; 196 197 /* 0: mask, 1: unmask */ 198 reg = COMMON_INT_MASK_1; 199 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, reg); 200 201 reg = COMMON_INT_MASK_2; 202 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, reg); 203 204 reg = COMMON_INT_MASK_3; 205 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, reg); 206 207 reg = COMMON_INT_MASK_4; 208 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 209 210 reg = INT_STA_MASK; 211 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 212 } 213 214 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 215 { 216 u32 reg; 217 218 /* 0: mask, 1: unmask */ 219 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4); 220 reg &= ~COMMON_INT_MASK_4; 221 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 222 223 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK); 224 reg &= ~INT_STA_MASK; 225 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 226 } 227 228 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 229 { 230 u32 reg; 231 232 /* 0: mask, 1: unmask */ 233 reg = COMMON_INT_MASK_4; 234 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 235 236 reg = INT_STA_MASK; 237 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 238 } 239 240 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 241 { 242 u32 reg; 243 244 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 245 if (reg & PLL_LOCK) 246 return PLL_LOCKED; 247 else 248 return PLL_UNLOCKED; 249 } 250 251 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 252 { 253 u32 reg; 254 255 if (enable) { 256 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 257 reg |= DP_PLL_PD; 258 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 259 } else { 260 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 261 reg &= ~DP_PLL_PD; 262 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 263 } 264 } 265 266 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 267 enum analog_power_block block, 268 bool enable) 269 { 270 u32 reg; 271 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 272 273 if (dp->plat_data.dev_type == ROCKCHIP_DP) 274 phy_pd_addr = ANALOGIX_DP_PD; 275 276 switch (block) { 277 case AUX_BLOCK: 278 if (enable) { 279 reg = analogix_dp_read(dp, phy_pd_addr); 280 reg |= AUX_PD; 281 analogix_dp_write(dp, phy_pd_addr, reg); 282 } else { 283 reg = analogix_dp_read(dp, phy_pd_addr); 284 reg &= ~AUX_PD; 285 analogix_dp_write(dp, phy_pd_addr, reg); 286 } 287 break; 288 case CH0_BLOCK: 289 if (enable) { 290 reg = analogix_dp_read(dp, phy_pd_addr); 291 reg |= CH0_PD; 292 analogix_dp_write(dp, phy_pd_addr, reg); 293 } else { 294 reg = analogix_dp_read(dp, phy_pd_addr); 295 reg &= ~CH0_PD; 296 analogix_dp_write(dp, phy_pd_addr, reg); 297 } 298 break; 299 case CH1_BLOCK: 300 if (enable) { 301 reg = analogix_dp_read(dp, phy_pd_addr); 302 reg |= CH1_PD; 303 analogix_dp_write(dp, phy_pd_addr, reg); 304 } else { 305 reg = analogix_dp_read(dp, phy_pd_addr); 306 reg &= ~CH1_PD; 307 analogix_dp_write(dp, phy_pd_addr, reg); 308 } 309 break; 310 case CH2_BLOCK: 311 if (enable) { 312 reg = analogix_dp_read(dp, phy_pd_addr); 313 reg |= CH2_PD; 314 analogix_dp_write(dp, phy_pd_addr, reg); 315 } else { 316 reg = analogix_dp_read(dp, phy_pd_addr); 317 reg &= ~CH2_PD; 318 analogix_dp_write(dp, phy_pd_addr, reg); 319 } 320 break; 321 case CH3_BLOCK: 322 if (enable) { 323 reg = analogix_dp_read(dp, phy_pd_addr); 324 reg |= CH3_PD; 325 analogix_dp_write(dp, phy_pd_addr, reg); 326 } else { 327 reg = analogix_dp_read(dp, phy_pd_addr); 328 reg &= ~CH3_PD; 329 analogix_dp_write(dp, phy_pd_addr, reg); 330 } 331 break; 332 case ANALOG_TOTAL: 333 if (enable) { 334 reg = analogix_dp_read(dp, phy_pd_addr); 335 reg |= DP_PHY_PD; 336 analogix_dp_write(dp, phy_pd_addr, reg); 337 } else { 338 reg = analogix_dp_read(dp, phy_pd_addr); 339 reg &= ~DP_PHY_PD; 340 analogix_dp_write(dp, phy_pd_addr, reg); 341 } 342 break; 343 case POWER_ALL: 344 if (enable) { 345 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | 346 CH1_PD | CH0_PD; 347 analogix_dp_write(dp, phy_pd_addr, reg); 348 } else { 349 analogix_dp_write(dp, phy_pd_addr, 0x00); 350 } 351 break; 352 default: 353 break; 354 } 355 } 356 357 void analogix_dp_init_analog_func(struct analogix_dp_device *dp) 358 { 359 u32 reg; 360 int timeout_loop = 0; 361 362 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 363 364 reg = PLL_LOCK_CHG; 365 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 366 367 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 368 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 369 analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg); 370 371 /* Power up PLL */ 372 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 373 analogix_dp_set_pll_power_down(dp, 0); 374 375 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 376 timeout_loop++; 377 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 378 dev_err(dp->dev, 379 "failed to get pll lock status\n"); 380 return; 381 } 382 udelay(20); 383 } 384 } 385 386 /* Enable Serdes FIFO function and Link symbol clock domain module */ 387 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 388 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 389 | AUX_FUNC_EN_N); 390 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 391 } 392 393 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 394 { 395 u32 reg; 396 397 if (dm_gpio_is_valid(&dp->hpd_gpio)) 398 return; 399 400 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 401 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, reg); 402 403 reg = INT_HPD; 404 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 405 } 406 407 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 408 { 409 u32 reg; 410 411 if (dm_gpio_is_valid(&dp->hpd_gpio)) 412 return; 413 414 analogix_dp_clear_hotplug_interrupts(dp); 415 416 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 417 reg &= ~(F_HPD | HPD_CTRL); 418 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 419 } 420 421 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 422 { 423 u32 reg; 424 425 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 426 reg |= (F_HPD | HPD_CTRL); 427 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 428 } 429 430 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 431 { 432 u32 reg; 433 434 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 435 reg = dm_gpio_get_value(&dp->hpd_gpio); 436 if (reg) 437 return DP_IRQ_TYPE_HP_CABLE_IN; 438 else 439 return DP_IRQ_TYPE_HP_CABLE_OUT; 440 } else { 441 /* Parse hotplug interrupt status register */ 442 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4); 443 444 if (reg & PLUG) 445 return DP_IRQ_TYPE_HP_CABLE_IN; 446 447 if (reg & HPD_LOST) 448 return DP_IRQ_TYPE_HP_CABLE_OUT; 449 450 if (reg & HOTPLUG_CHG) 451 return DP_IRQ_TYPE_HP_CHANGE; 452 453 return DP_IRQ_TYPE_UNKNOWN; 454 } 455 } 456 457 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 458 { 459 u32 reg; 460 461 /* Disable AUX channel module */ 462 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 463 reg |= AUX_FUNC_EN_N; 464 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 465 } 466 467 void analogix_dp_init_aux(struct analogix_dp_device *dp) 468 { 469 u32 reg; 470 471 /* Clear inerrupts related to AUX channel */ 472 reg = RPLY_RECEIV | AUX_ERR; 473 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 474 475 analogix_dp_reset_aux(dp); 476 477 /* Disable AUX transaction H/W retry */ 478 if (dp->plat_data.dev_type == ROCKCHIP_DP) 479 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | 480 AUX_HW_RETRY_COUNT_SEL(3) | 481 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 482 else 483 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | 484 AUX_HW_RETRY_COUNT_SEL(0) | 485 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 486 analogix_dp_write(dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, reg); 487 488 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 489 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 490 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, reg); 491 492 /* Enable AUX channel module */ 493 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 494 reg &= ~AUX_FUNC_EN_N; 495 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 496 } 497 498 int analogix_dp_detect(struct analogix_dp_device *dp) 499 { 500 u32 reg; 501 502 if (dm_gpio_is_valid(&dp->hpd_gpio)) 503 return dm_gpio_get_value(&dp->hpd_gpio); 504 505 if (dp->force_hpd) 506 analogix_dp_force_hpd(dp); 507 508 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 509 if (reg & HPD_STATUS) 510 return 1; 511 512 return 0; 513 } 514 515 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 516 { 517 u32 reg; 518 519 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 520 reg &= ~SW_FUNC_EN_N; 521 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 522 } 523 524 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) 525 { 526 int reg; 527 int retval = 0; 528 int timeout_loop = 0; 529 530 /* Enable AUX CH operation */ 531 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 532 reg |= AUX_EN; 533 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 534 535 /* Is AUX CH command reply received? */ 536 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 537 while (!(reg & RPLY_RECEIV)) { 538 timeout_loop++; 539 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 540 dev_err(dp->dev, "AUX CH command reply failed!\n"); 541 return -ETIMEDOUT; 542 } 543 544 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 545 udelay(11); 546 } 547 548 /* Clear interrupt source for AUX CH command reply */ 549 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 550 551 /* Clear interrupt source for AUX CH access error */ 552 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 553 if (reg & AUX_ERR) { 554 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR); 555 return -EREMOTEIO; 556 } 557 558 /* Check AUX CH error access status */ 559 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA); 560 if ((reg & AUX_STATUS_MASK) != 0) { 561 dev_err(dp->dev, 562 "AUX CH error happens: %d\n", reg & AUX_STATUS_MASK); 563 return -EREMOTEIO; 564 } 565 566 return retval; 567 } 568 569 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 570 unsigned int reg_addr, 571 unsigned char data) 572 { 573 u32 reg; 574 int i; 575 int retval; 576 577 for (i = 0; i < 3; i++) { 578 /* Clear AUX CH data buffer */ 579 reg = BUF_CLR; 580 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 581 582 /* Select DPCD device address */ 583 reg = AUX_ADDR_7_0(reg_addr); 584 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 585 reg = AUX_ADDR_15_8(reg_addr); 586 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 587 reg = AUX_ADDR_19_16(reg_addr); 588 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 589 590 /* Write data buffer */ 591 reg = (unsigned int)data; 592 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg); 593 594 /* 595 * Set DisplayPort transaction and write 1 byte 596 * If bit 3 is 1, DisplayPort transaction. 597 * If Bit 3 is 0, I2C transaction. 598 */ 599 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 600 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 601 602 /* Start AUX transaction */ 603 retval = analogix_dp_start_aux_transaction(dp); 604 if (retval == 0) 605 break; 606 } 607 608 return retval; 609 } 610 611 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 612 unsigned int reg_addr, 613 unsigned char *data) 614 { 615 u32 reg; 616 int i; 617 int retval; 618 619 for (i = 0; i < 3; i++) { 620 /* Clear AUX CH data buffer */ 621 reg = BUF_CLR; 622 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 623 624 /* Select DPCD device address */ 625 reg = AUX_ADDR_7_0(reg_addr); 626 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 627 reg = AUX_ADDR_15_8(reg_addr); 628 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 629 reg = AUX_ADDR_19_16(reg_addr); 630 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 631 632 /* 633 * Set DisplayPort transaction and read 1 byte 634 * If bit 3 is 1, DisplayPort transaction. 635 * If Bit 3 is 0, I2C transaction. 636 */ 637 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 638 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 639 640 /* Start AUX transaction */ 641 retval = analogix_dp_start_aux_transaction(dp); 642 if (retval == 0) 643 break; 644 } 645 646 /* Read data buffer */ 647 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 648 *data = (unsigned char)(reg & 0xff); 649 650 return retval; 651 } 652 653 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 654 unsigned int reg_addr, 655 unsigned int count, 656 unsigned char data[]) 657 { 658 u32 reg; 659 unsigned int start_offset; 660 unsigned int cur_data_count; 661 unsigned int cur_data_idx; 662 int i; 663 int retval = 0; 664 665 /* Clear AUX CH data buffer */ 666 reg = BUF_CLR; 667 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 668 669 start_offset = 0; 670 while (start_offset < count) { 671 /* Buffer size of AUX CH is 16 * 4bytes */ 672 if ((count - start_offset) > 16) 673 cur_data_count = 16; 674 else 675 cur_data_count = count - start_offset; 676 677 for (i = 0; i < 3; i++) { 678 /* Select DPCD device address */ 679 reg = AUX_ADDR_7_0(reg_addr + start_offset); 680 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 681 reg = AUX_ADDR_15_8(reg_addr + start_offset); 682 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 683 reg = AUX_ADDR_19_16(reg_addr + start_offset); 684 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 685 686 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 687 cur_data_idx++) { 688 reg = data[start_offset + cur_data_idx]; 689 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0 + 690 4 * cur_data_idx, reg); 691 } 692 693 /* 694 * Set DisplayPort transaction and write 695 * If bit 3 is 1, DisplayPort transaction. 696 * If Bit 3 is 0, I2C transaction. 697 */ 698 reg = AUX_LENGTH(cur_data_count) | 699 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 700 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 701 702 /* Start AUX transaction */ 703 retval = analogix_dp_start_aux_transaction(dp); 704 if (retval == 0) 705 break; 706 } 707 708 start_offset += cur_data_count; 709 } 710 711 return retval; 712 } 713 714 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 715 unsigned int reg_addr, 716 unsigned int count, 717 unsigned char data[]) 718 { 719 u32 reg; 720 unsigned int start_offset; 721 unsigned int cur_data_count; 722 unsigned int cur_data_idx; 723 int i; 724 int retval = 0; 725 726 /* Clear AUX CH data buffer */ 727 reg = BUF_CLR; 728 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 729 730 start_offset = 0; 731 while (start_offset < count) { 732 /* Buffer size of AUX CH is 16 * 4bytes */ 733 if ((count - start_offset) > 16) 734 cur_data_count = 16; 735 else 736 cur_data_count = count - start_offset; 737 738 /* AUX CH Request Transaction process */ 739 for (i = 0; i < 3; i++) { 740 /* Select DPCD device address */ 741 reg = AUX_ADDR_7_0(reg_addr + start_offset); 742 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 743 reg = AUX_ADDR_15_8(reg_addr + start_offset); 744 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 745 reg = AUX_ADDR_19_16(reg_addr + start_offset); 746 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 747 748 /* 749 * Set DisplayPort transaction and read 750 * If bit 3 is 1, DisplayPort transaction. 751 * If Bit 3 is 0, I2C transaction. 752 */ 753 reg = AUX_LENGTH(cur_data_count) | 754 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 755 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 756 757 /* Start AUX transaction */ 758 retval = analogix_dp_start_aux_transaction(dp); 759 if (retval == 0) 760 break; 761 } 762 763 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 764 cur_data_idx++) { 765 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 766 + 4 * cur_data_idx); 767 data[start_offset + cur_data_idx] = 768 (unsigned char)reg; 769 } 770 771 start_offset += cur_data_count; 772 } 773 774 return retval; 775 } 776 777 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 778 unsigned int device_addr, 779 unsigned int reg_addr) 780 { 781 u32 reg; 782 int retval; 783 784 /* Set EDID device address */ 785 reg = device_addr; 786 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 787 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, 0x0); 788 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, 0x0); 789 790 /* Set offset from base address of EDID device */ 791 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg_addr); 792 793 /* 794 * Set I2C transaction and write address 795 * If bit 3 is 1, DisplayPort transaction. 796 * If Bit 3 is 0, I2C transaction. 797 */ 798 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 799 AUX_TX_COMM_WRITE; 800 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 801 802 /* Start AUX transaction */ 803 retval = analogix_dp_start_aux_transaction(dp); 804 if (retval < 0) 805 return retval; 806 807 return 0; 808 } 809 810 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 811 unsigned int device_addr, 812 unsigned int reg_addr, 813 unsigned int *data) 814 { 815 u32 reg; 816 int i; 817 int retval; 818 819 for (i = 0; i < 3; i++) { 820 /* Clear AUX CH data buffer */ 821 reg = BUF_CLR; 822 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 823 824 /* Select EDID device */ 825 retval = analogix_dp_select_i2c_device(dp, device_addr, 826 reg_addr); 827 if (retval != 0) 828 continue; 829 830 /* 831 * Set I2C transaction and read data 832 * If bit 3 is 1, DisplayPort transaction. 833 * If Bit 3 is 0, I2C transaction. 834 */ 835 reg = AUX_TX_COMM_I2C_TRANSACTION | 836 AUX_TX_COMM_READ; 837 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 838 839 /* Start AUX transaction */ 840 retval = analogix_dp_start_aux_transaction(dp); 841 if (retval == 0) 842 break; 843 } 844 845 /* Read data */ 846 if (retval == 0) 847 *data = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 848 849 return retval; 850 } 851 852 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 853 unsigned int device_addr, 854 unsigned int reg_addr, 855 unsigned int count, 856 unsigned char edid[]) 857 { 858 u32 reg; 859 unsigned int i, j; 860 unsigned int cur_data_idx; 861 unsigned int defer = 0; 862 int retval = 0; 863 864 for (i = 0; i < count; i += 16) { 865 for (j = 0; j < 3; j++) { 866 /* Clear AUX CH data buffer */ 867 reg = BUF_CLR; 868 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 869 870 /* Set normal AUX CH command */ 871 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 872 reg &= ~ADDR_ONLY; 873 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 874 875 /* 876 * If Rx sends defer, Tx sends only reads 877 * request without sending address 878 */ 879 if (!defer) 880 retval = analogix_dp_select_i2c_device(dp, 881 device_addr, reg_addr + i); 882 else 883 defer = 0; 884 885 if (retval == 0) { 886 /* 887 * Set I2C transaction and write data 888 * If bit 3 is 1, DisplayPort transaction. 889 * If Bit 3 is 0, I2C transaction. 890 */ 891 reg = AUX_LENGTH(16) | 892 AUX_TX_COMM_I2C_TRANSACTION | 893 AUX_TX_COMM_READ; 894 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, 895 reg); 896 897 /* Start AUX transaction */ 898 retval = analogix_dp_start_aux_transaction(dp); 899 if (retval == 0) 900 break; 901 } 902 /* Check if Rx sends defer */ 903 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM); 904 if (reg == AUX_RX_COMM_AUX_DEFER || 905 reg == AUX_RX_COMM_I2C_DEFER) { 906 dev_dbg(dp->dev, "Defer: %d\n\n", reg); 907 defer = 1; 908 } 909 } 910 911 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 912 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 913 + 4 * cur_data_idx); 914 edid[i + cur_data_idx] = (unsigned char)reg; 915 } 916 } 917 918 return retval; 919 } 920 921 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 922 { 923 u32 reg; 924 925 reg = bwtype; 926 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) 927 analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg); 928 } 929 930 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 931 { 932 u32 reg; 933 934 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_BW_SET); 935 *bwtype = reg; 936 } 937 938 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 939 { 940 u32 reg; 941 942 reg = count; 943 analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg); 944 } 945 946 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 947 { 948 u32 reg; 949 950 reg = analogix_dp_read(dp, ANALOGIX_DP_LANE_COUNT_SET); 951 *count = reg; 952 } 953 954 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 955 bool enable) 956 { 957 u32 reg; 958 959 if (enable) { 960 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 961 reg |= ENHANCED; 962 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 963 } else { 964 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 965 reg &= ~ENHANCED; 966 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 967 } 968 } 969 970 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 971 enum pattern_set pattern) 972 { 973 u32 reg; 974 975 switch (pattern) { 976 case PRBS7: 977 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 978 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 979 break; 980 case D10_2: 981 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 982 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 983 break; 984 case TRAINING_PTN1: 985 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 986 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 987 break; 988 case TRAINING_PTN2: 989 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 990 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 991 break; 992 case DP_NONE: 993 reg = SCRAMBLING_ENABLE | 994 LINK_QUAL_PATTERN_SET_DISABLE | 995 SW_TRAINING_PATTERN_SET_NORMAL; 996 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 997 break; 998 default: 999 break; 1000 } 1001 } 1002 1003 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, 1004 u32 level) 1005 { 1006 u32 reg; 1007 1008 reg = analogix_dp_read(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 1009 reg &= ~PRE_EMPHASIS_SET_MASK; 1010 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1011 analogix_dp_write(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL, reg); 1012 } 1013 1014 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, 1015 u32 level) 1016 { 1017 u32 reg; 1018 1019 reg = analogix_dp_read(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1020 reg &= ~PRE_EMPHASIS_SET_MASK; 1021 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1022 analogix_dp_write(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL, reg); 1023 } 1024 1025 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, 1026 u32 level) 1027 { 1028 u32 reg; 1029 1030 reg = analogix_dp_read(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1031 reg &= ~PRE_EMPHASIS_SET_MASK; 1032 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1033 analogix_dp_write(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL, reg); 1034 } 1035 1036 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, 1037 u32 level) 1038 { 1039 u32 reg; 1040 1041 reg = analogix_dp_read(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1042 reg &= ~PRE_EMPHASIS_SET_MASK; 1043 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1044 analogix_dp_write(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL, reg); 1045 } 1046 1047 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, 1048 u32 training_lane) 1049 { 1050 u32 reg; 1051 1052 reg = training_lane; 1053 analogix_dp_write(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL, reg); 1054 } 1055 1056 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, 1057 u32 training_lane) 1058 { 1059 u32 reg; 1060 1061 reg = training_lane; 1062 analogix_dp_write(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL, reg); 1063 } 1064 1065 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, 1066 u32 training_lane) 1067 { 1068 u32 reg; 1069 1070 reg = training_lane; 1071 analogix_dp_write(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL, reg); 1072 } 1073 1074 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, 1075 u32 training_lane) 1076 { 1077 u32 reg; 1078 1079 reg = training_lane; 1080 analogix_dp_write(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL, reg); 1081 } 1082 1083 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp) 1084 { 1085 u32 reg; 1086 1087 reg = analogix_dp_read(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 1088 return reg; 1089 } 1090 1091 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp) 1092 { 1093 u32 reg; 1094 1095 reg = analogix_dp_read(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1096 return reg; 1097 } 1098 1099 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp) 1100 { 1101 u32 reg; 1102 1103 reg = analogix_dp_read(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1104 return reg; 1105 } 1106 1107 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp) 1108 { 1109 u32 reg; 1110 1111 reg = analogix_dp_read(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1112 return reg; 1113 } 1114 1115 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 1116 { 1117 u32 reg; 1118 1119 reg = analogix_dp_read(dp, ANALOGIX_DP_PHY_TEST); 1120 reg |= MACRO_RST; 1121 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1122 1123 /* 10 us is the minimum reset time. */ 1124 udelay(20); 1125 1126 reg &= ~MACRO_RST; 1127 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1128 } 1129 1130 void analogix_dp_init_video(struct analogix_dp_device *dp) 1131 { 1132 u32 reg; 1133 1134 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 1135 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 1136 1137 reg = 0x0; 1138 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1139 1140 reg = CHA_CRI(4) | CHA_CTRL; 1141 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1142 1143 reg = 0x0; 1144 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1145 1146 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 1147 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg); 1148 } 1149 1150 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 1151 { 1152 u32 reg; 1153 1154 /* Configure the input color depth, color space, dynamic range */ 1155 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 1156 (dp->video_info.color_depth << IN_BPC_SHIFT) | 1157 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 1158 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_2, reg); 1159 1160 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 1161 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3); 1162 reg &= ~IN_YC_COEFFI_MASK; 1163 if (dp->video_info.ycbcr_coeff) 1164 reg |= IN_YC_COEFFI_ITU709; 1165 else 1166 reg |= IN_YC_COEFFI_ITU601; 1167 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, reg); 1168 } 1169 1170 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 1171 { 1172 u32 reg; 1173 1174 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1175 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1176 1177 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1178 1179 if (!(reg & DET_STA)) 1180 return -EINVAL; 1181 1182 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1183 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1184 1185 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1186 1187 if (reg & CHA_STA) 1188 return -EINVAL; 1189 1190 return 0; 1191 } 1192 1193 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 1194 enum clock_recovery_m_value_type type, 1195 u32 m_value, u32 n_value) 1196 { 1197 u32 reg; 1198 1199 if (type == REGISTER_M) { 1200 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1201 reg |= FIX_M_VID; 1202 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1203 reg = m_value & 0xff; 1204 analogix_dp_write(dp, ANALOGIX_DP_M_VID_0, reg); 1205 reg = (m_value >> 8) & 0xff; 1206 analogix_dp_write(dp, ANALOGIX_DP_M_VID_1, reg); 1207 reg = (m_value >> 16) & 0xff; 1208 analogix_dp_write(dp, ANALOGIX_DP_M_VID_2, reg); 1209 1210 reg = n_value & 0xff; 1211 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, reg); 1212 reg = (n_value >> 8) & 0xff; 1213 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, reg); 1214 reg = (n_value >> 16) & 0xff; 1215 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, reg); 1216 } else { 1217 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1218 reg &= ~FIX_M_VID; 1219 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1220 1221 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00); 1222 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80); 1223 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00); 1224 } 1225 } 1226 1227 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 1228 { 1229 u32 reg; 1230 1231 if (type == VIDEO_TIMING_FROM_CAPTURE) { 1232 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1233 reg &= ~FORMAT_SEL; 1234 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1235 } else { 1236 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1237 reg |= FORMAT_SEL; 1238 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1239 } 1240 } 1241 1242 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 1243 { 1244 u32 reg; 1245 1246 if (enable) { 1247 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1248 reg &= ~VIDEO_MODE_MASK; 1249 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 1250 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1251 } else { 1252 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1253 reg &= ~VIDEO_MODE_MASK; 1254 reg |= VIDEO_MODE_SLAVE_MODE; 1255 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1256 } 1257 } 1258 1259 void analogix_dp_start_video(struct analogix_dp_device *dp) 1260 { 1261 u32 reg; 1262 1263 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 1264 reg |= VIDEO_EN; 1265 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 1266 } 1267 1268 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 1269 { 1270 u32 reg; 1271 1272 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1273 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1274 1275 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1276 if (!(reg & STRM_VALID)) 1277 return -EINVAL; 1278 1279 return 0; 1280 } 1281 1282 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 1283 { 1284 u32 reg; 1285 1286 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 1287 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 1288 reg |= MASTER_VID_FUNC_EN_N; 1289 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 1290 1291 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1292 reg &= ~INTERACE_SCAN_CFG; 1293 reg |= (dp->video_info.interlaced << 2); 1294 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1295 1296 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1297 reg &= ~VSYNC_POLARITY_CFG; 1298 reg |= (dp->video_info.v_sync_polarity << 1); 1299 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1300 1301 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1302 reg &= ~HSYNC_POLARITY_CFG; 1303 reg |= (dp->video_info.h_sync_polarity << 0); 1304 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1305 1306 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 1307 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1308 } 1309 1310 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 1311 { 1312 u32 reg; 1313 1314 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1315 reg &= ~SCRAMBLING_DISABLE; 1316 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1317 } 1318 1319 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 1320 { 1321 u32 reg; 1322 1323 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1324 reg |= SCRAMBLING_DISABLE; 1325 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1326 } 1327